An output of a first amplifier is coupled to an input of a first track and hold circuit and an input of a second track and hold circuit. An input of a first summing circuit is also coupled to an output of the first track and hold circuit and an output of the second track and hold circuit. In addition, an input of a second summing circuit is coupled to the output of the first track and hold circuit and the output of the second track and hold circuit. Moreover, an input of a third summing circuit coupled to an output of a modulator and an output of the second summing circuit, and an output of the third summing circuit coupled to an input of the first amplifier.

An output of a first amplifier is coupled to an input of a first track and hold circuit and an input of a second track and hold circuit. An input of a first summing circuit is also coupled to an output of the first track and hold circuit and an output of the second track and hold circuit. In addition, an input of a second summing circuit is coupled to the output of the first track and hold circuit and the output of the second track and hold circuit. Moreover, an input of a third summing circuit coupled to an output of a modulator and an output of the second summing circuit, and an output of the third summing circuit coupled to an input of the first amplifier.

There is provided a chopper stabilized amplifier with an input bias current reduced. The chopper stabilized amplifier includes a main amplifier and a correction circuit. The correction circuit includes a second gm amplifier of a full differential type. A first selector and the second gm amplifier are coupled to each other without DC blocking capacitors. The differential input state of the second gm amplifier is configured with a depletion-type transistor.

In a general aspect, a system can include a fully differential amplifier circuit that includes a first amplifier, and first and second feedback paths. The first feedback path can provide a feedback path from a positive output of the first amplifier to a negative input of the first amplifier. The second feedback path can provide a feedback path from a negative output of the first amplifier to a positive input of the first amplifier. The system can include a chopper clock circuit configured to output a variable duty cycle chopper clock signal. The system can include a common mode loop circuit including a second amplifier and chopper switches. The common mode loop circuit can be configured as a local feedback loop for the first amplifier. The chopper switches can be configured to receive the chopper clock signal and control current flow into the positive and negative inputs.

A chopper amplifying circuit employing a negative impedance compensation technique, including a differential input end, a first-level chopper switch, a first-level amplifying circuit, a second-level chopper switch, a second-level amplifying circuit, a negative impedance converting circuit, a negative feedback unit, an input capacitor, and a differential output end, is provided. The differential input end is connected to the first-level chopper switch. An output terminal of the first-level chopper switch is connected to the first-level amplifying circuit through the input capacitor. The first-level amplifying circuit is connected to the second-level chopper switch, which is connected to the second-level amplifying circuit. The second-level amplifying circuit is connected to the differential output end, and is also connected to a feedback input end of the first-level amplifying circuit through the negative feedback unit. The negative impedance converting circuit is parallel-connected to a signal input end of the first-level amplifying circuit.

Amplifying circuitry configured such that when a detection circuit detects an abnormal state in which the level of signals input to a main amplifying circuit exceeds a normal range, a control circuit sets the state of integration of signals in the integration circuit to a default state. When the detection circuit detects the abnormal state and then detects that an operating state returns to a normal state in which the level of signals input to the main amplifying circuit is included in the normal range, the control circuit cancels the setting of the default state in the integration circuit.

An apparatus may include a delta sigma modulator. A first portion of the delta sigma modulator may form a digital predictor while a second portion of the delta sigma modulator may form an analog approximator. An output of the analog approximator may be coupled with a quantizer. The digital predictor, the analog approximator, and the quantizer may form a digitizing loop configured to convert an analog input into a digital output. The digital predictor may be configured to generate, based on a polarity of one or more digital outputs from the quantizer, a digital prediction of an expected amplitude of the analog input. The quantizer may be configured to respond to the digital prediction by adjusting a dynamic range of the digitizing loop including by changing a quantization step size used by the quantizer to quantize the analog input. Related methods are also provided.

A magnetic operational amplifier having a differential stage includes a first magnetic field effect transistor MAGFET and a differential signal conditioner, the differential signal conditioner including a load stage, a differential input pair connected to the load stage and a biasing current source connected to the differential input pair; the magnetic field effect transistor MAGFET being connected to the load stage as a second differential input pair and the differential signal conditioner including a second biasing current source connected to the magnetic field effect transistor MAGFET.

An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.

In a general aspect, a current sense amplifier circuit (CSA) can include a null amplifier path and a main amplifier path that are both configured to receive a differential input voltage. The null amplifier path can output a first differential output voltage based on the differential input voltage. The main amplifier path can also be configured to receive the first differential output voltage and output a second differential output voltage based on the differential input voltage and the first differential output voltage. The null and main amplifier paths can each include a differential amplifier having first and second input stages that are each configured to receive the differential input voltage. The first input stage and the second input stage of the main amplifier path can and be powered by a respective (first and second) floating voltage supply rails that are referenced to a floating ground rail.