Apparatus and methods for digitally-assisted feedback offset correction are provided herein. In certain configurations, an amplifier includes amplification circuitry for providing amplification to an input signal and chopping circuitry for compensating for an input offset voltage of the amplifier. Additionally, the amplifier further includes a digitally-assisted feedback offset correction circuit, which includes a chopping ripple detection circuit, a feedback-path chopping circuit, a digital correction control circuit, and an offset correction circuit. The chopping ripple detection circuit generates a detected ripple signal based on detecting an output ripple of the amplifier. Additionally, the feedback-path chopping circuit demodulates the detected ripple signal using the amplifier's chopping clock signal. The digital correction control circuit receives the demodulated ripple signal, which the digital correction control circuit uses to control a value of a digital offset control signal that controls an amount of input offset correction provided by the offset correction circuit.

A biosignal apparatus is described including an amplifier and a sampler. The amplifier is configured to alternate between an operating state and a low power state based on a periodically changing control signal. The sampler is configured to sample a signal output from the amplifier in response to the amplifier being in the operating state and maintain the sampled signal in response to the amplifier being in the low power state.

A biosignal apparatus is described including an amplifier and a sampler. The amplifier is configured to alternate between an operating state and a low power state based on a periodically changing control signal. The sampler is configured to sample a signal output from the amplifier in response to the amplifier being in the operating state and maintain the sampled signal in response to the amplifier being in the low power state.

A signal amplifying circuit with noise suppression function includes a first circuit module and a second circuit module. The first circuit module includes a current source and a switch. The current source is connected to an input stage for inputting a current. The switch is connected to a first output terminal and adapted to switch the input stage and the first output terminal according to a chopping frequency. The second circuit module includes an equivalent capacitance disposed between an output stage and a second input terminal connected to the first output terminal. The signal amplifying circuit controls current volume of the current source and capacity value of the equivalent capacitance to accordingly adjust an interior frequency bandwidth of the signal amplifying circuit, and the interior frequency bandwidth is smaller than the chopping frequency and greater than an input signal of the input stage.

A chopper stabilzed amplifier with synchronous switched capacitor noise filtering is disclosed. In an exemplary embodiment, an apparatus includes a chopper amplifier having an input that receives an input signal and an output that outputs an amplified signal. The chopper amplifier includes an input chopping circuit and an output chopping circuit, where the input and output chopping circuits operate in response to a chop clock. The apparatus also includes a switched capacitor filter having an input that receives the amplified signal and an output that outputs a filtered signal. The switched capacitor filter operates in response to a filter clock. The apparatus also includes a filter timing adjuster that receives a reference voltage and adjusts a phase of the filter clock with respect to the chop clock to reduce chopper noise on that reference voltage.

A chopper stabilzed amplifier with synchronous switched capacitor noise filtering is disclosed. In an exemplary embodiment, an apparatus includes a chopper amplifier having an input that receives an input signal and an output that outputs an amplified signal. The chopper amplifier includes an input chopping circuit and an output chopping circuit, where the input and output chopping circuits operate in response to a chop clock. The apparatus also includes a switched capacitor filter having an input that receives the amplified signal and an output that outputs a filtered signal. The switched capacitor filter operates in response to a filter clock. The apparatus also includes a filter timing adjuster that receives a reference voltage and adjusts a phase of the filter clock with respect to the chop clock to reduce chopper noise on that reference voltage.

Various apparatuses and methods are described where a signal is amplified using a chopper amplifier arrangement, and ripples caused by said chopper amplifier arrangement are reduced. In some cases, this reduction of ripples is performed by controlling a voltage offset of an amplifier of said chopper amplifier arrangement. In other embodiments, a detection of ripples or a chopping of the chopper amplifier arrangement is at least temporarily disabled.

Various apparatuses and methods are described where a signal is amplified using a chopper amplifier arrangement, and ripples caused by said chopper amplifier arrangement are reduced. In some cases, this reduction of ripples is performed by controlling a voltage offset of an amplifier of said chopper amplifier arrangement. In other embodiments, a detection of ripples or a chopping of the chopper amplifier arrangement is at least temporarily disabled.

Embodiments herein provide various apparatuses and techniques to reduce flicker noise and voltage offset from the buffers and/or amplifiers while avoiding additional alias components in a sampled-data receiver with chopper stabilization. Additionally, a direct-conversion baseband chain may be improved by disposing alternating current (AC) coupling circuits between chopper circuits in the transmitter or receiver chain to enable selection of a distinct common-mode level at each stage of the direct-conversion chain, while reducing or eliminating signal loss at direct current (DC) frequencies.

Embodiments herein provide various apparatuses and techniques to reduce flicker noise and voltage offset from the buffers and/or amplifiers while avoiding additional alias components in a sampled-data receiver with chopper stabilization. Additionally, a direct-conversion baseband chain may be improved by disposing alternating current (AC) coupling circuits between chopper circuits in the transmitter or receiver chain to enable selection of a distinct common-mode level at each stage of the direct-conversion chain, while reducing or eliminating signal loss at direct current (DC) frequencies.