An ultrasonic imaging system is described in which a column-row-parallel architecture is provided at the circuit level of an ultrasonic transceiver. The ultrasonic imaging system can include a NM array of transducer elements and a plurality of transceiver circuits where each transceiver circuit is connected to a corresponding one transducer element of the NM array of transducer elements. A shared pulser gate driver and a shared VGA is provided for each row and column. Selection logic includes row select, column select, and per-element bit select. Through the column-row-parallel architecture, a variety of aperture configurations can be achieved.

A bidirectional data link includes a forward channel transmitter circuit and a forward channel receiver circuit. The forward channel transmitter circuit includes a forward channel driver circuit, and a back channel receiver circuit. The back channel receiver circuit is coupled to the forward channel driver circuit. The back channel receiver circuit includes a summation circuit and an active filter circuit. The summation circuit is coupled to the forward channel driver circuit. The active filter circuit is coupled to the summation circuit. The forward channel receiver circuit includes a forward channel receiver, and a back channel driver circuit. The back channel driver circuit is coupled to the forward channel receiver.

A fingerprint sensing circuit and a fingerprint sensing apparatus are provided. The fingerprint sensing circuit includes a sensing electrode; a first converting circuit connected to the sensing electrode and configured to convert a coupling capacitance sensed by the sensing electrode into a drive voltage, where the drive voltage is equal to a sum of a voltage variation converted from the coupling capacitance and a reference voltage; and a second converting circuit configured to generate a sensing current based on the drive voltage, and send the sensing current to a fingerprint signal processor, where the sensing current is equal to a product of a transconductance gain of the second converting circuit and the voltage variation, and the fingerprint signal processor performs fingerprint sensing based on the sensing current. With the fingerprint sensing circuit and the fingerprint sensing apparatus, the detection accuracy can be improved.

The present invention provides a differential to single-ended converter including a first input node, a second input node, an operational amplifier and a feedback circuit. The operational amplifier has a first terminal and a second terminal, wherein the first terminal of the operational amplifier receives a first signal from the first input terminal, and the second terminal of the operational amplifier receives a second signal from the second input terminal. The feedback circuit is configured to receive an output signal of the operational amplifier and generate a first feedback signal to the first terminal of the operational amplifier to reduce a swing of the first signal, and generate a second feedback signal to the second terminal of the operational amplifier to balance noises induced by the feedback circuit and inputted to the first terminal and the second terminal.

To provide a semiconductor device that makes it possible to reduce a cell circuit area and an increase in resolution. There is provided a semiconductor device including: a first region in which readout cells are arranged in an array form, the readout cells having one of input transistors included in a differential amplifier: and a second region in which reference cells are arranged in an array form, the reference cells having another input transistor included in the differential amplifier, the first region and the second region being separated from each other.

An amplifier circuit is provided, which includes an input stage circuit, at least one impedance component and a current supply circuit, where the input stage circuit is coupled between at least one input terminal of the amplifier circuit and at least one output terminal of the amplifier circuit, the impedance component is coupled between a first reference voltage and the output terminal, and the current supply circuit is coupled between a second reference voltage and the output terminal. The input stage circuit is arranged to generate a signal current in response to an input signal on the input terminal, and the current supply circuit is arranged to provide at least one adjustment current. In addition, a common mode voltage level of an output signal on the output terminal is controlled by the adjustment current, to allow the amplifier circuit to perform low voltage operations.

A system for a differential trans-impedance amplifier circuit comprising: an amplifier having a pair of input nodes and configured to generate an amplified replica of a differential voltage on said pair of input nodes; a photodiode; a pair of capacitors coupling said photodiode to said pair of input nodes; at least one resistance coupled between said pair of input nodes of said amplifier; and a bias network comprising two photodiode biasing resistances each photodiode biasing resistance coupled in series between said photodiode and a respective DC voltage. A feedback loop for the amplifier may include source followers that are operable to level shift voltages prior to coupling capacitors that couple said photodiode to said amplifier to ensure stable bias conditions for said amplifier. The source followers may include CMOS transistors. The amplifier may be integrated in a complementary metal-oxide semiconductor (CMOS) chip, which may include a CMOS photonics chip.

A chopper amplifier circuit includes a first amplifier path with chopper circuitry, a switched-capacitor filter, and multiple gain stages. The chopper amplifier circuit also includes a second amplifier path with a feed-forward gain stage. A chopping frequency of the chopper circuitry is greater than a threshold frequency at which the second amplifier path is used instead of the first amplifier path.

Radio Frequency (RF) amplifier design with RFIC suffers gain variations from gain variations due to wafer process variations, temperature changes, and supply voltage changes. Three methods are proposed to achieve constant amplifier gain, either through on-chip wafer calibration, or self-calibration. Through automatic adjustment of amplifier bias current, the proposed methods maintain constant amplifier gain over process, temperature, supply voltage variations. Under the proposed Method 1, a constant transconductance Gm with enhanced gain accuracy is maintained via wafer calibration. Under the proposed Method 2, a constant transconductance Gm is maintained by time-domain averaging through different transistors. Under the proposed Method 3, a constant Gm*R or RF gain is maintained considering the impedance of a matching network of the RF amplifier.

A first terminal receives a first DC voltage. A switch selectively couples the first terminal to a second terminal providing an output. A control circuit selectively actuates the switch in response to a comparison of the first DC voltage to a second DC voltage. A low-dropout (LDO) linear voltage regulator, connected between the first and third terminals, operates to provide the second DC voltage from the first DC voltage.