An apparatus has four transistors. The first and third transistors each have a gate coupled to a first input terminal and second input terminal respectively, a source coupled to a current source and to a first terminal of a bias voltage source, and a substrate coupled to a second terminal of the bias voltage source. The second and fourth transistors each have a gate coupled to the first input terminal and the second input terminal respectively, a source coupled to the drain of the first and third transistors respectively, a drain coupled to a lower voltage supply and a substrate coupled to its source. The bias voltage source increases the threshold voltages of the first and third transistors above the second and fourth transistors, respectively. This ensures that the first and third transistors turn on after the second and fourth transistors, respectively.

A circuit device includes a detection signal terminal to which a detection signal from a vibrator is input, a digital signal terminal that performs at least one of an input and an output of a digital signal, a detection circuit, and a signal generation circuit that generates a noise reduction signal based on the digital signal. The detection circuit includes an amplification circuit that amplifies the detection signal. The amplification circuit performs addition processing of a signal obtained by amplifying the detection signal and the noise reduction signal.

Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, an apparatus may include a memory cell, a differential amplifier having a first input node, a second input node, and an output node that is coupled with the first input node via a first capacitor, and a second capacitor coupled with the first input node. The apparatus may include a controller configured to cause the apparatus to bias the first capacitor, couple the memory cell with the first input node, and generate, at the output node, a sense signal based at least in part on biasing the first capacitor and coupling the memory cell with the first input node. The apparatus may also include a sense component configured to determine a logic state stored by the memory cell based at least in part on the sense signal.

A differential amplifier circuit includes a first and second amplifiers that output a differential signal in a radio-frequency band, a first inductor having a first end connected to an output end of the first amplifier, a second inductor having a first end connected to an output end of the second amplifier, a choke inductor connected to second ends of the first and second inductors, a first and second capacitors, and a switch that connects the second capacitor in parallel to the first capacitor or terminates a parallel connection of the first and second capacitors. A resonant circuit formed by connecting the first or second inductor in series with the first capacitor has a different resonant frequency from a resonant circuit formed by connecting the first or second inductor in series with the parallel-connected first and second capacitors. These resonant frequencies correspond to second harmonic frequencies of the differential signal.

Radio Frequency (RF) amplifier design with RFIC suffers gain variations from gain variations due to wafer process variations, temperature changes, and supply voltage changes. Three methods are proposed to achieve constant amplifier gain, either through on-chip wafer calibration, or self-calibration. Through automatic adjustment of amplifier bias current, the proposed methods maintain constant amplifier gain over process, temperature, supply voltage variations. Under the proposed Method 1, a constant transconductance Gm with enhanced gain accuracy is maintained via wafer calibration. Under the proposed Method 2, a constant transconductance Gm is maintained by time-domain averaging through different transistors. Under the proposed Method 3, a constant Gm*R or RF gain is maintained considering the impedance of a matching network of the RF amplifier.

An operational amplifier includes a first output transistor and a second output transistor connected in series between two power nodes, the second output transistor having a semiconductor type opposite to the first output transistor, the first output transistor and the second output transistor being electrically coupled at an output node, and gates of the first output transistor and the second output transistor being connected to a first drive node and a second drive node respectively; and a decoupling capacitor circuit electrically connected between the first drive node and the second drive node.

Linearity is improved in an amplifier circuit without lowering gain. The amplifier circuit includes a transistor, a load, an impedance element, and a variable current source. The transistor amplifies an input signal. The load is connected between the transistor and a power supply. The impedance element is connected between the transistor and a ground terminal, and passes a direct current. The variable current source is connected to a connection part between the transistor and the impedance element, and supplies a current in accordance with a voltage of the connection part.

Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, an apparatus may include a memory cell, a differential amplifier having a first input node, a second input node, and an output node that is coupled with the first input node via a first capacitor, and a second capacitor coupled with the first input node. The apparatus may include a controller configured to cause the apparatus to bias the first capacitor, couple the memory cell with the first input node, and generate, at the output node, a sense signal based at least in part on biasing the first capacitor and coupling the memory cell with the first input node. The apparatus may also include a sense component configured to determine a logic state stored by the memory tell based at least in part on the sense signal.

A parallel input and dynamic cascaded OTA (operational transconductance amplifier includes: plural sub-OTAs which generate corresponding plural transconductance output currents according to corresponding plural differential input voltages; and at least one cascading capacitor which is cascaded between a first sub-OTA and a second sub-OTA. A second transconductance output current generated by the second sub-OTA is coupled through the cascading capacitor to generate a transient bias current on a common mode bias node of the first sub-OTA, thus providing the transient bias current to a differential pair circuit of the first sub-OTA in a case when a transient variation occurs in the differential input voltage corresponding to the first sub-OTA, so that a loop bandwidth and a response speed during a transient state are enhanced.

Provided is a track-and-hold circuit capable of reducing the power consumption of a differential amplifier circuit while preserving the broadband nature (without narrowing the bandwidth). In the track-and-hold circuit 1 including a differential amplifier circuit 10, a switch circuit 20, and a hold capacitor C.sub.21, the differential amplifier circuit 10 includes a first resistor R.sub.11 having one end connected to a collector electrode of a first transistor Q.sub.11 constituting a differential pair, a second resistor R.sub.12 having one end connected to the collector electrode of a second transistor Q.sub.12 constituting the differential pair, and a third resistor R.sub.13 to which the other end of the first resistor R.sub.11 and the other end of the second resistor R.sub.12 are connected and which is connected between the other ends and a power supply V.sub.CC.