Variations in a receiving circuit employing differential signaling are reduced. The receiving circuit converts a first signal and a second signal which are supplied through differential signaling into a third signal which is a single-ended signal and outputs the third signal. The receiving circuit includes an operational amplifier, a first element, a first transistor, and a first circuit. The first element is connected to the first circuit through a first node to which the first transistor is connected. The first signal and the second signal that is the inverse of the first signal are supplied to the operational amplifier. The operational amplifier supplies an output signal to the first element, and a first preset potential is supplied to the first node through the first transistor. A signal including variations of the operational amplifier is stored in the first element in accordance with the first preset potential. The first circuit that is supplied with the first preset potential determines an initial value of the third signal without being influenced by the signal including variations of the operational amplifier.

An amplifier circuit is provided, which includes an input stage circuit, at least one impedance component and a current supply circuit, where the input stage circuit is coupled between at least one input terminal of the amplifier circuit and at least one output terminal of the amplifier circuit, the impedance component is coupled between a first reference voltage and the output terminal, and the current supply circuit is coupled between a second reference voltage and the output terminal. The input stage circuit is arranged to generate a signal current in response to an input signal on the input terminal, and the current supply circuit is arranged to provide at least one adjustment current. In addition, a common mode voltage level of an output signal on the output terminal is controlled by the adjustment current, to allow the amplifier circuit to perform low voltage operations.

An exemplary embodiment of the invention relates to an electrical amplifier comprising a differential preamplifier having a first output port and a second output port; and a downstream amplifier stage having a first output unit and a second output unit; wherein the first output unit is connected to the first output port of the differential preamplifier and the second output unit is connected to the second output port of the differential preamplifier; and wherein a negative impedance converter is electrically located in at least one of said differential preamplifier and said downstream amplifier stage.

An apparatus for canceling an input offset of a receiver including a differential amplification unit and a differential comparison unit in a distance sensing system includes: an output monitoring unit selectively monitoring differential outputs of the differential comparison unit and the differential amplification unit; a current type digital-analog conversion unit connected to each of an input terminal of the differential comparison unit and the input terminal of the differential amplification unit; and a control unit controlling the current type digital-analog conversion unit to reduce a difference in differential output of the differential comparison unit according to a comparison result for the difference of the monitored differential output of the differential comparison unit and controlling the current type digital-analog conversion unit to reduce the difference in differential output of the differential amplification unit according to the comparison result for the difference of the monitored differential output of the differential amplification unit.

A low noise amplifier includes a preamplifier, first differential amplifiers, second differential amplifiers, a signal adder, and a load circuit. The preamplifier receives an input signal, and amplifies the input signal to generate a first signal. The input signal and the first signal have the same phase. The first differential amplifiers receive the first signal and a first reference signal and generate a first output differential signal pair. The second differential amplifiers receive the input signal and a second reference signal and generate a second output differential signal pair. The signal adder adds up the first output differential signal pair and the second output differential signal pair. The load circuit is coupled to the signal adder, and generates a third output differential signal pair according to the addition result.

Linearity is improved in an amplifier circuit without lowering gain.

The amplifier circuit includes a transistor, a load, an impedance element, and a variable current source. The transistor amplifies an input signal. The load is connected between the transistor and a power supply. The impedance element is connected between the transistor and a ground terminal, and passes a direct current. The variable current source is connected to a connection part between the transistor and the impedance element, and supplies a current in accordance with a voltage of the connection part.

An amplifier circuit includes a primary differential amplifier circuit connected to receive a differential input and provide a primary differential output with a first non-linearity. A secondary differential amplifier circuit is connected to receive the differential input. The secondary differential amplifier circuit is configured to generate a secondary differential output with a second non-linearity. The secondary differential output and the primary differential output are coupled together with opposing polarities such that the second non-linearity cancels out at least the first non-linearity.

Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, an apparatus may include a memory cell, a differential amplifier having a first input node, a second input node, and an output node that is coupled with the first input node via a first capacitor, and a second capacitor coupled with the first input node. The apparatus may include a controller configured to cause the apparatus to bias the first capacitor, couple the memory cell with the first input node, and generate, at the output node, a sense signal based at least in part on biasing the first capacitor and coupling the memory cell with the first input node. The apparatus may also include a sense component configured to determine a logic state stored by the memory cell based at least in part on the sense signal.

A bi-directional amplifier (BDA) comprises a first pair of amplifier transistors and a second pair of amplifier transistors, wherein the first pair of amplifier transistors are cross-coupled with the second pair of amplifier transistors, and wherein the first pair of amplifier transistors and the second pair of amplifier transistors each comprise a differential common-emitter (CE) pair (or common-source (CS) pair) with equal transistor size or different transistor size. The BDA further comprises a plurality of blocking capacitors to decouple the collector and the base biases of the first pair of amplifier transistors and the second pair of amplifier transistors. Alternatively or additionally, the BDA further comprises two input/output baluns, through which a common voltage bias is applied to the collectors of each of the differential CE pairs (or drains of CS pairs in some implementations). The baluns enable single-ended measurement and characterization.

The present application discloses a transconductance amplifier and a related chip. The transconductance amplifier is configured to generate an output current according to a positive input voltage and a negative input voltage, wherein the transconductance amplifier includes: an input stage, configured to receive the positive input voltage and the negative input voltage and generate a positive output current and a negative output current, wherein the input stage includes: a first transistor, wherein a gate thereof is coupled to the positive input voltage; a second transistor, wherein a gate thereof is coupled to the negative input voltage; a first resistor, serially connected between the first transistor and the second transistor; a third transistor, wherein a source of the third transistor is coupled between the first resistor and the first transistor, and a drain of the third transistor is configured to output the positive output current; and a fourth transistor