Systems and methods disclosed herein provide a coupled T-coil circuit for differential mode bandwidth extension and common mode rejection. The coupled T-coil circuit includes a first layer including at least a first portion of a first T-coil circuit and a first portion of a second T-coil circuit, and a second layer disposed on top of the first layer and interconnected to the first layer, the second layer including at least a second portion of the first T-coil circuit and a second portion of the second T-coil circuit. The first T-coil circuit includes one or more first coils with a first wind direction. The second T-coil circuit comprises one or more second coils with a second wind direction. The first wind direction can be opposite the second wind direction.

At least some embodiments are directed to a system comprising a capacitor coupled to a voltage supply rail and configured to carry a capacitor current that comprises first and second parts. The capacitor current is an alternating current (AC). A first current mirror component may couple to the capacitor and to the voltage supply rail and is configured to carry the first part of the capacitor current. A second current mirror component couples to the voltage supply rail and is configured to carry the second part of the capacitor current. The second part of the capacitor current is proportionally related to the first part of the capacitor current. A circuit couples to the second current mirror component. The capacitor and the first and second current mirror components are configured to attenuate a common mode noise current flowing to the circuit.

A switched capacitor circuit includes a first main sampler circuit, a second main sampler circuit, a first replica sampler circuit, and a second replica sampler circuit. The first main sampler circuit samples a first input of a differential input, and generates a first output corresponding to the sampled first input based on a first reference voltage. The second main sampler circuit samples a second input of the differential input, and generates a second output corresponding to the sampled second input based on a second reference voltage. The first replica sampler circuit receives the first input, and holds the received first input based on the second reference voltage. The second replica sampler circuit receives the second input, and holds the received second input based on the first reference voltage.

An offset cancellation circuit and method are provided where successive stages of cascaded amplifiers are operated in a saturated state. Biasing is provided, by a feedback amplifier, connected in a feedback loop for each cascaded amplifier, so as to be responsive, in a non-saturated state, to the input of an associated amplifier stage operating in the saturated state.

Provided is an amplifier circuit including an inverting input terminal configured to receive a first voltage, an output terminal, and a class A amplifier circuit configured to generate, at the output terminal, an output voltage that changes in reverse polarity with respect to the first voltage, in which a bias current of an output stage of the class A amplifier circuit changes according to the first voltage.

A signal amplifier includes a first amplifier, a second amplifier, and an output. The first amplifier amplifies a first input signal to form a first amplified output signal. The first input signal has a common mode voltage in a first voltage range, and the first amplified output signal has a common mode voltage in a second voltage range different from the first voltage range. The second amplifier amplifies a second input signal to form a second amplified output signal. The first input signal has the common mode voltage in the second voltage range and the second amplified output signal has the common mode voltage in the second voltage range. The output outputs the first amplified output signal or the second amplified output signal as an amplified output signal.

A comparator includes a resolver controlled by a resolver clock signal and a differential amplifier controlled by a sampling clock signal. The resolver clock signal and the sampling clock signal are such that amplification at the differential amplifier during the reset phase of the resolver clock signal and the reset phase of the sampling clock signal begins during the resolving phase of the resolver.

An equalizer, in at least some embodiments, comprises an amplifier configured to produce an amplified voltage signal that is a function of an ambient temperature affecting the equalizer. The equalizer also includes a linear equalizer stage coupled to the amplifier and comprising a transistor having a resistance controlled by the amplified voltage signal. The linear equalizer stage is configured to produce a voltage output signal having a gain that is dependent on the transistor resistance and on a frequency of the amplified voltage signal.

The present invention is directed to electrical circuits and techniques thereof. More specifically, an embodiment of the present invention provides a line driver with transistors directly coupled to the ground, and a bias voltage is coupled common mode resistors of the line driver. There are other embodiments as well.

The present invention provides an amplifier circuit, wherein the amplifier circuit includes an operational amplifier and a feedback path. The operational amplifier has an input terminal and an output terminal, and is arranged for receiving an input signal to generate an output signal. The feedback path is coupled between the input terminal and the output terminal of the operational amplifier, wherein the feedback path comprises at least two poly resistors, and a depletion region of at least one of the two poly resistors is biased by the output signal generated by the operational amplifier.