A multi-bit digital signal that is generated by modulating a baseband signal by a modulation circuit and includes components in a radio frequency band is amplified by switch-mode amplifiers (100-1, 100-2) on a bit-by-bit basis, amplified signals are band-limited by frequency-variable variable band limiting units (201-1, 201-2) and thereafter subjected to voltage-to-current conversion by voltage/current source conversion units (202-1, 202-2) provided with variable capacitances, the signals converted to current are synthesized at a synthesis point X, and a resultant signal is impedance-corrected by an impedance correction unit (203) and output as a transmission signal to an antenna of a load (300). Consequently, the present invention provides a transmitter capable of synthesizing output signals from a plurality of switch-mode amplifiers and transmitting a resultant signal while maintaining an impedance characteristic with respect to a plurality of transmit frequencies without increasing a circuit size.

A semiconductor device includes: a semiconductor substrate whose contour is a pentagon; a front-stage amplifier formed relatively near a vertex of the pentagon of the semiconductor substrate; and a rear-stage amplifier formed relatively near a side opposed to the vertex of the semiconductor substrate and amplifying an output from the front-stage amplifier.

Apparatus and methods for an improved-efficiency Doherty amplifier are described. The Doherty amplifier may include a two-stage peaking amplifier that transitions from an “off” state to an “on” state later and more rapidly than a single-stage peaking amplifier used in a conventional Doherty amplifier. The improved Doherty amplifier may operate at higher gain values than a conventional Doherty amplifier, with no appreciable reduction in signal bandwidth.

A high frequency signal amplifying circuitry of an embodiment includes a first splitter, a first amplifier, a second amplifier, a loop oscillation suppressor, and a combiner. The first amplifier includes a second splitter, a first carrier amplifier, a first peak amplifier, and a first combiner. The second amplifier includes a third splitter, a second carrier amplifier, a second peak amplifier, and a second combiner. The second carrier amplifier being adjacent to an associated the first carrier amplifier or the second peak amplifier being adjacent to an associated the first peak amplifier. The loop oscillation suppressor located between the second carrier amplifier and the associated first carrier amplifier or the second peak amplifier and the associated first peak amplifier.

Distributed amplifiers with controllable linearization are provided herein. In certain embodiments, a distributed amplifier includes a differential input transmission line, a differential output transmission line, and a plurality of differential distributed amplifier stages connected between the differential input transmission line and the differential output transmission line at different points or nodes. The distributed amplifier further includes a differential non-linearity cancellation stage connected between the differential input transmission line and the differential output transmission line and providing signal inversion relative to the differential distributed amplifier stages. The differential non-linearity cancellation stage operates with a separately controllable bias from the differential distributed amplifier stages, thereby providing a mechanism to control the linearity of the distributed amplifier.

Apparatus and methods for an inverted Doherty amplifier operating at gigahertz frequencies are described. RF fractional bandwidth and signal bandwidth may be increased over a conventional Doherty amplifier configuration when impedance-matching components and an impedance inverter in an output network of the inverted Doherty amplifier are designed based on characteristics of the main and peaking amplifier and asymmetry factor of the amplifier.

An on-chip transformer circuit is disclosed. The on-chip transformer circuit comprises a primary winding circuit comprising at least one turn of a primary conductive winding arranged as a first N-sided polygon in a first dielectric layer of a substrate; and a secondary winding circuit comprising at least one turn of a secondary conductive winding arranged as a second N-sided polygon in a second, different, dielectric layer of the substrate. In some embodiments, the primary winding circuit and the secondary winding circuit are arranged to overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding, wherein the predetermined locations comprise a number of locations less than all locations along the primary conductive winding and the secondary conductive winding.

A high-frequency power amplifier apparatus includes: a plurality of amplifiers that respectively amplify a plurality of distributed signals obtained by distributing a high-frequency signal of a predetermined frequency, the amplifiers respectively outputting a plurality of amplified signals; and a cavity-type high-frequency power combiner having a cavity surrounded by a conductor wall, the cavity-type high-frequency power combiner combining together power of the plurality of amplified signals in the cavity by operating in a TE.sub.011 resonance mode with a resonance frequency equal to the predetermined frequency.

Transformer-based Doherty power amplifier (PA). In some embodiments, a Doherty PA can include a carrier amplification path having an output that includes a carrier transformer, and a peaking amplification path having an output that includes a peaking transformer. The Doherty PA can further include a combiner configured to combine the outputs of the carrier and peaking amplification paths into an output node. The combiner can include a quarter-wave circuit implemented between the carrier and peaking transformers.

An embodiment of a Doherty amplifier module includes a substrate, an RF signal splitter, a carrier amplifier die, and a peaking amplifier die. The RF signal splitter divides an input RF signal into first and second input RF signals, and conveys the first and second input RF signals to first and second splitter output terminals. The carrier amplifier die includes one or more first power transistors configured to amplify, along a carrier signal path, the first input RF signal to produce an amplified first RF signal. The peaking amplifier die includes one or more second power transistors configured to amplify, along a peaking signal path, the second input RF signal to produce an amplified second RF signal. The carrier and peaking amplifier die are coupled to the substrate so that the RF signal paths through the carrier and peaking amplifier die extend in substantially different (e.g., orthogonal) directions.