An amplifier includes amplifier circuits connected in series between a ground and a power supply, each amplifier circuit includes: a transistor; and a first capacitance, one end of which is connected to a drain of the transistor, a first amplifier circuit connected closest to the power supply includes a load connected between the drain of the transistor and the power supply, each of the amplifier circuits except for the first amplifier circuit includes a load connected between the drain of the transistor of an own amplifier circuit and a source of the transistor of an amplifier circuit adjacent to the own amplifier circuit, each of the amplifier circuits except for an amplifier circuit connected farthest from the power supply includes a second capacitance connected between the source of the transistor and the ground, and the second capacitance has a capacitance value larger than a capacitance value of the first capacitance.

A multiple-path amplifier (e.g., a Doherty amplifier) includes a semiconductor die, a radio frequency (RF) signal input terminal, a combining node structure integrally formed with the semiconductor die, and first and second amplifiers (e.g., main and peaking amplifiers) integrally formed with the die. Inputs of the first and second amplifiers are electrically coupled to the RF signal input terminal. A plurality of wirebonds is connected between an output of the first amplifier and the combining node structure. An output of the second amplifier is electrically coupled to the combining node structure (e.g., through a conductive path with a negligible phase delay). A phase delay between the outputs of the first and second amplifiers is substantially equal to 90 degrees. The second amplifier may be divided into two amplifier portions that are physically located on opposite sides of the first amplifier.

A Class-F power amplifier includes a harmonic matching network topology comprised of circuit elements configured relative to an output network of the power amplifier. The harmonic matching network topology suppresses higher-order harmonics in such a power amplifier and includes coupled-line capacitors and open-stubs that introduce harmonic terminations in the output network, and quarter-wavelength transmission lines to match an overall network to a 50-ohm output load. The harmonic matching network topology enables the power amplifier to exhibit desired performance characteristics in specific frequency ranges for high-power applications.

A power amplifier includes: plural amplifiers; a tournament-tree-shaped circuit connected with the plural amplifiers and including plural transmission lines arranged in a tournament-tree shape; and plural difference frequency short circuits shunt-connected with plural nodes of the tournament-tree-shaped circuit, wherein each of the plural difference frequency short circuits includes an inductor and a capacitor connected in series, resonant frequencies of the plural difference frequency short circuits become lower as the plural difference frequency short circuits are more separated from the plural amplifiers, and the difference frequency short circuits having equivalent resonant frequencies are connected with plural nodes in the same stage among the plural nodes.

Apparatus and methods for an inverted Doherty amplifier operating at gigahertz frequencies are described. RF fractional bandwidth and signal bandwidth may be increased over a conventional Doherty amplifier configuration when impedance-matching components and an impedance inverter in an output network of the inverted Doherty amplifier are designed based on characteristics of the main and peaking amplifier and asymmetry factor of the amplifier.

Apparatus and methods for an inverted Doherty amplifier operating at gigahertz frequencies are described. RF fractional bandwidth and signal bandwidth may be increased over a conventional Doherty amplifier configuration when impedance-matching components and an impedance inverter in an output network of the inverted Doherty amplifier are designed based on characteristics of the main and peaking amplifier and asymmetry factor of the amplifier.

An on-chip transformer circuit is disclosed. The on-chip transformer circuit comprises a primary winding circuit comprising at least one turn of a primary conductive winding arranged as a first N-sided polygon in a first dielectric layer of a substrate; and a secondary winding circuit comprising at least one turn of a secondary conductive winding arranged as a second N-sided polygon in a second, different, dielectric layer of the substrate. In some embodiments, the primary winding circuit and the secondary winding circuit are arranged to overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding, wherein the predetermined locations comprise a number of locations less than all locations along the primary conductive winding and the secondary conductive winding.

A Doherty amplifier module includes a substrate, an RF signal splitter, a carrier amplifier die, and first and second peaking amplifier dies. The RF signal splitter divides an input RF signal into first, second, and third input RF signals, and conveys the input RF signals to splitter output terminals. The carrier amplifier die includes one or more first power transistors configured to amplify, along a carrier signal path, the first input RF signal to produce an amplified first RF signal. The peaking amplifier dies each include one or more additional power transistors configured to amplify, along first and second peaking signal paths, the second and third input RF signals to produce amplified second and third RF signals. The dies are coupled to the substrate so that the RF signal paths through the carrier and one or more of the peaking amplifier dies extend in substantially different (e.g., orthogonal) directions.

Distributed amplifiers with controllable linearization are provided herein. In certain embodiments, a distributed amplifier includes a differential input transmission line, a differential output transmission line, and a plurality of differential distributed amplifier stages connected between the differential input transmission line and the differential output transmission line at different points or nodes. The distributed amplifier further includes a differential non-linearity cancellation stage connected between the differential input transmission line and the differential output transmission line and providing signal inversion relative to the differential distributed amplifier stages. The differential non-linearity cancellation stage operates with a separately controllable bias from the differential distributed amplifier stages, thereby providing a mechanism to control the linearity of the distributed amplifier.

Apparatus and methods for an inverted Doherty amplifier operating at gigahertz frequencies are described. RF fractional bandwidth and signal bandwidth may be increased over a conventional Doherty amplifier configuration when impedance-matching components and an impedance inverter in an output network of the inverted Doherty amplifier are designed based on characteristics of the main and peaking amplifier and asymmetry factor of the amplifier.