A transimpedance amplifier includes a variable gain circuit configured to generate a pair of complementary signals in accordance with an input signal and a reference signal. A first differential circuit of the variable gain circuit includes a first transistor including a control terminal to receive the input signal, a second transistor including a control terminal to receive the reference signal, and a variable resistance circuit including a first field effect transistor (FET) and a second FET. A first timing when a voltage of a first linearity adjustment signal input to the first FET reaches a first threshold voltage of the first FET and a second timing when a voltage of a second linearity adjustment signal input to the second FET reaches a second threshold voltage of the second FET are different from each other.

LNA circuitry includes an input node, and output node, a primary amplifier stage, a first ancillary amplifier stage, and an input gain selection switch. The primary amplifier stage is configured to provide a first gain response between a primary amplifier stage input node and a primary amplifier stage output node, wherein the primary amplifier stage input node is coupled to the input node and the primary amplifier stage output node is coupled to the output node. The first ancillary amplifier stage is configured to provide a second gain response between a first ancillary amplifier stage input node and a first ancillary amplifier stage output node, wherein the first ancillary amplifier stage output node is coupled to the primary amplifier stage output node. The input gain selection switch is coupled between the input node and the first ancillary amplifier stage input node.

An instrumentation amplifier configured for providing high common mode rejection is described and includes an input differential stage configured to receive a differential input voltage and a folded cascode amplifying stage configured to receive output current mode signals provided from the input differential pair. A plurality of feedback networks is provided to improve the input stage. The amplifier may operate to provide an enhanced common mode rejection ratio of a single gain block in the instrumentation amplifier. In some examples, the circuitry may have a differential folded cascode amplifying stage which permits high precision and low distortion of amplified signals without degrading the common mode rejection ratio.

Systems, methods and apparatus for efficient power control of an RF amplifier for amplification of a constant envelope RF signal are described. A reduction in a size of a pass device of an LDO regulator is obtained by removing the pass device of the LDO regulator from a main current conduction path of the RF amplifier. Power control is provided by varying one or more gate voltages to cascoded transistors of a transistor stack of the RF amplifier according to a power control voltage. Various configurations for controlling the gate voltages are presented by way of a smaller size LDO regulator or by completely removing the LDO regulator. In a case where a supply voltage to the transistor stack varies, such as in a case of a battery, a compensation circuit is used to adjust the power control voltage in view of a variation of the supply voltage, and therefore null a corresponding drift in output power of the RF amplifier.

An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.

Methods and devices for amplifying an input RF signal according to at least two gain-states is described. According to one aspect, a multi gain amplifier circuit including a low noise amplifier having a stack of transistors is used for amplification of the input RF signal. When switching from a low gain-state to a high gain-state, the drain-to-source voltage of the output transistor of the stack is increased to affect region of operation of the output transistor, and thereby reduce non-linearity at the output of the amplifier. When switching from the high gain-state to the low gain-state, the drain-to-source voltage of the input transistor of the stack is increased to affect region of operation of the input transistor, and thereby reduce non-linearity at the output of the amplifier.

An amplifier circuit including a first folded double cascode stage configured to receive a differential input signal at a first pair of input transistors and generate a first drive signal, a second folded double cascode stage configured to receive the differential input signal at a second pair of input transistors and generate a second drive signal, and an output stage. The output stage includes a PMOS common-source output transistor configured to receive the first drive signal at its gate, and an NMOS common-source output transistor configured to receive the first drive signal at its gate, the PMOS common-source output transistor and NMOS common-source output transistor being jointly configured to generate an output signal based on the first drive signal and the second drive signal.

Aspects of the disclosure relate to a radio frequency phase shifter. An example includes an amplification stage to produce an amplified voltage, the amplification stage having a first amplifier with a first input coupled to a first output of a hybrid coupler and a second amplifier with a complementary second input coupled to a complementary second output of the hybrid coupler. A vector modulation stage coupled to the amplification stage receives the amplified voltage and produces a modulated vector, the vector modulation stage has an in-phase section and a quadrature section to control the phase of the modulated vector in response to a phase control signal. A varactor coupled across the first input and the second input of the amplification stage adjusts the capacitance between the first input and the second input in response to a capacitance control signal.

According to one embodiment, a signal processing circuit includes a first voltage setting circuit that sets a reference voltage on an input side of an isolator, a variable gain amplifier circuit that amplifies an output signal of the isolator, a DC offset adjustment circuit that adjusts an offset of the variable gain amplifier circuit, a second voltage setting circuit that sets a reference voltage on an output side of the isolator, and a control circuit that controls the DC offset adjustment circuit in response to a result of comparison of an output voltage of the variable gain amplifier circuit with an output voltage of the second voltage setting circuit.

In accordance with an embodiment, an integrated circuit includes a substrate, an amplifier MOSFET, and a bias voltage terminal configured to generate a potential difference of the substrate relative to at least one load terminal of the amplifier MOSFET.