A variable gain amplifying circuit incorporates an operational amplifier, an input device, a feedback device, a transconductance circuit, and a dynamic biasing circuit. The operational amplifier has an output terminal providing an amplified difference output signal. The input device has a first terminal receiving a first input signal, and a second terminal coupled to a first input terminal of the operational amplifier. The feedback device is coupled between the first input terminal of the operational amplifier and the output terminal of the operational amplifier. The dynamic biasing circuit generates a bias current to according to a set value. The transconductance circuit converts the difference between the first input signal and a second input signal into an analog output current flowing through the feedback device. The analog output current of the transconductance circuit is varied according to the bias current.

In high speed communication applications, e.g., optical communication, a variable gain amplifier is used for input signal amplitude normalization or for linear equalization. Traditionally a bipolar Gilbert multiplier circuit is used. When moving towards a low-power application, a modified circuit topology is implemented to reduce the minimum supply voltage requirement of the variable gain amplifier while ensuring that bias current levels remain substantially the same and achieving the same current switching capacity as the traditional circuit. As a result, the power consumption of the circuit can be greatly reduced. The modified circuit topology combines the amplifier and gain transistors and achieves gain programming using a voltage difference of two pairs of floating voltage sources.

A variable gain amplifier having stabilized frequency response for widened gain control range. A resistor-capacitor compensation network is provided between two differential current input ports and corresponding emitter nodes of cross-coupled four transistors in the variable gain amplifier to desensitize the gain control voltages to the system noise and provide compensation to the VGA frequency response when the differential gain control voltage varies the gain setting, yielding a substantially stabilized frequency response over a 3 dB bandwidth ranging from 1 GHz to 60 GHz with a widened gain control range up to 12 dB without increasing power consumption.

Disclosed examples include programmable gain amplifier (PGA) circuits with an operation amplifier circuit having a first amplifier input and a second amplifier input including a plurality of second input nodes, a resistor array including a plurality of resistor sections connected in series with one another between the amplifier output and a reference voltage node, and a trim select circuit coupled between the second amplifier input and the resistor array circuit to deliver a feedback voltage signal to each individual one of the second input nodes from a given selected one of a plurality of the tap points of the resistor array circuit according to a trim code to provide analog gain trimming by interpolation.

At least some embodiments are directed to a system comprising an amplifier containing a first bias current source and configured to provide an output voltage at a node, a gain stage coupled to the node and comprising a second bias current source, and a buffer stage coupled to the node and comprising third and fourth bias current sources and an additional set of bias current sources, the third and fourth bias current sources are able to activate output transistors that are configured to increase current provided to a load. The system also comprises a controller configured to activate the first bias current source, to activate the second bias current source after the first bias current source is activated, to activate the bias current sources in the set after the first bias current source is activated, and to activate the third and fourth bias current sources after the first and second bias current sources are activated and after the bias current sources in the set are activated.

A voltage gain amplifier (VGA) configured to have reduced supply noise. The VGA includes first resistor, first FET, and a first current-source coupled between first and second voltage rails. The VGA includes second resistor, second FET, and second current-source coupled between the voltage rails. A variable resistor is coupled between the respective sources of the first and second FETs. Variable capacitors are coupled between the first or a third voltage rail and the sources of the first and second input FETs, respectively. If capacitors are coupled to the first voltage rail, noise cancellation occurs across the gate-to-source voltages of the FETs if an input differential signal applied to the gates of the FETs is derived from a supply voltage at the first voltage rail. If capacitors are coupled to the third rail, supply noise is reduced if the supply voltage at the third rail is generated by a cleaner regulator.

A variable gain transconductance amplifier includes an amplifier transistor connected to an input node, a cascode transistor having a source connected to a drain of the amplifier transistor and having a drain connected to an output node, and a switching circuit connecting or disconnecting a node to which the amplifier transistor and the cascode transistor are connected to or from a fixed potential in a switchable manner. A variable gain circuit may include the variable gain transconductance amplifier.

Technologies are provided for variable gain amplifiers (VGAs). An example VGA includes a resistor ladder network comprising resistor legs coupled to a first plurality of resistors and a second plurality of resistors, a first set of differential switches connected to the resistor ladder network, a second set of differential switches connected to a set of output nodes, a third set of differential switches connected to the resistor ladder network, a fourth set of differential switches connected to the set of output nodes, and a fifth transistor and a sixth transistor comprising a differential pair coupled to a differential input signal. The fifth transistor is connected to the first set of differential switches and the sixth transistor connected to the third set of differential switches.

Disclosed examples include programmable gain amplifier (PGA) circuits with an operation amplifier circuit having a first amplifier input and a second amplifier input including a plurality of second input nodes, a resistor array including a plurality of resistor sections connected in series with one another between the amplifier output and a reference voltage node, and a trim select circuit coupled between the second amplifier input and the resistor array circuit to deliver a feedback voltage signal to each individual one of the second input nodes from a given selected one of a plurality of the tap points of the resistor array circuit according to a trim code to provide analog gain trimming by interpolation.

A voltage gain amplifier (VGA) configured to have reduced supply noise. The VGA includes first resistor, first FET, and a first current-source coupled between first and second voltage rails. The VGA includes second resistor, second FET, and second current-source coupled between the voltage rails. A variable resistor is coupled between the respective sources of the first and second FETs. Variable capacitors are coupled between the first or a third voltage rail and the sources of the first and second input FETs, respectively. If capacitors are coupled to the first voltage rail, noise cancellation occurs across the gate-to-source voltages of the FETs if an input differential signal applied to the gates of the FETs is derived from a supply voltage at the first voltage rail. If capacitors are coupled to the third rail, supply noise is reduced if the supply voltage at the third rail is generated by a cleaner regulator.