An output stage circuit of an operational amplifier, the operational amplifier, and a signal amplifying method applied to the operational amplifier are provided. The output stage circuit includes an inverting circuit and a compensation module. The inverting circuit is electrically connected to a gain stage circuit of the operational amplifier. The inverting circuit generates an output signal of the operational amplifier. The compensation module includes a first compensation circuit, including a first current providing path and a first suppression activation circuit. The first current providing path provides a first compensation current. The first suppression activation circuit conducts the first compensation current to the inverting circuit if a first compensation condition related to a first gain stage signal generated by the gain stage circuit is satisfied. Variation of the output signal is suppressed because of the first compensation current.

Certain aspects are directed to an amplifier. The amplifier generally includes a first transistor having a gate coupled to an input node of the amplifier, a source degeneration circuit, and a second transistor coupled between the source degeneration circuit and a source of the first transistor, a gate of the second transistor being configured to receive a gain control signal from a controller.

An analog signal buffer is disclosed. The analog signal buffer may include a transconductance cell and an active load. The active load may load the current from the transconductance cell with a PMOS transistor and an NMOS transistor and provide a feedback resistance. A transimpedance amplifier is disclosed. The transimpedance amplifier may include a first cell configured to receive a first signal and output a second signal and a second cell coupled to the first cell. The second cell may include an active feedback structure configured to couple an output of the second cell to an input of the second cell.

A low noise amplifier circuit includes an input stage circuit, a first output stage circuit, and a second output stage circuit. The input stage circuit is configured to receive an input signal and to generate a bias signal. The first output stage circuit corresponding to a first wireless communication and is configured to be biased according to the bias signal and a first control signal, in order to generate a first output signal, in which the first control signal is for setting a first gain of the first output stage circuit. The second output stage circuit corresponding to a second wireless communication and is configured to be biased according to the bias signal and a second control signal, in order to generate a second output signal, in which the second control signal is for setting a second gain of the second output stage circuit.

The present disclosure describes a method and system for linearizing an amplifier using transistor-level dynamic feedback. The method and system enables nonlinear amplifiers to exhibit linear performance using one or more of gain control elements and phase shifters in the feedback path. The disclosed method and system may also allow an amplifier to act as a pre-distorter or a frequency/gain programmable amplifier.

A gain equalizer and a method for controlling a tunable gain of the gain equalizer are provided. The gain equalizer includes a common source stage and a switch array. The common source stage is configured to apply the tunable gain to an input signal, in order to generate an amplified signal. The common source stage includes input transistors and cascode transistors, wherein the cascode transistors are respectively coupled to the input transistors. The input transistors are configured to receive the input signal via gate terminals of the input transistors, respectively, and the cascode transistors are configured to output the amplified signal via drain terminals of the cascode transistors, respectively. In addition, the switch array is coupled between respective source terminals of the cascode transistors, wherein the tunable gain is controlled according to an equivalent impedance of the switch array.

Provided in the present invention is an automatic gain control method for a burst-mode transimpedance amplifier. A transistor is connected in parallel at either end of a feedback resistor of a transimpedance amplifier. A gate-source voltage of the transistor is controlled by detecting and then reversely amplifying an output voltage of the transimpedance amplifier. The present invention also provides a circuit implementing the method, obviates the need for support from any particular process, and is implementable using conventional components.

A CMOS trans-impedance amplifier includes an inverting amplifier circuit and a feedback resistor. The inverting amplifier circuit includes an input end and an output end, and the feedback resistor is coupled therebetween. The inverting amplifier circuit includes at least three sequentially-connected amplifier units, and each amplifier unit includes at least three sequentially-connected nFETs, namely an input signal receiving part nFET, an intermediate part nFET and a DC signal receiving part nFET. A common connection terminal of the input signal receiving part nFET and the intermediate part nFET is configured to output an amplified voltage signal.

Variable gain amplifiers (VGA) with output phase invariance are provided herein. In certain embodiments, a VGA is operable in a selected gain setting chosen from multiple gain settings that provide different amounts of amplification to a radio frequency (RF) input signal. The VGA includes a gain transistor that has a substantially constant bias current across the gain settings, such that the VGA's output phase, input impedance matching, and/or input return loss are substantially constant. The gain setting of the VGA is selected by controlling relative biasing of a pair of cascode transistors each connected to the gain transistor by a corresponding degeneration resistor. The degeneration resistors provide compensation that reduces or eliminates a difference in output phase of the VGA across gain settings, for instance, by introducing a zero in a transfer function of the VGA that cancels a pole arising from the cascode transistors.

A gain modulation circuit includes a load circuit, a differential circuit, a current source, a resistor, a first transistor, and a detector circuit. The load circuit is configured to receive a supply voltage. The differential circuit is coupled to the load circuit. The differential circuit and the load circuit are configured to generate a pair of output voltages according to a pair of input voltages and the supply voltage. The current source is coupled to the differential circuit. The resistor is coupled to the differential circuit and the current source. The first transistor is coupled to the differential circuit. The detector circuit is configured to generate a detection signal according to the pair of input voltages. A turned-on degree of the first transistor is adjusted based on the detection signal, to adjust a linear region of the gain modulation circuit.