A dc coupled amplifier includes a pre-driver, and amplifier and a bias control circuit. The pre-driver is configured to receive one or more input signals and amplify the one or more input signals to create one or more pre-amplified signals. The amplifier has cascode configured transistors configured to receive and amplify the one or more pre-amplified signals to create one or more amplified signals, the amplifier further having an output driver termination element. The bias control circuit is connected between the pre-driver and the amplifier, the bias control circuit receiving at least one bias current from the output driver termination element of the amplifier, wherein the pre-driver, the amplifier and the bias control circuit are all formed on a same die.

An output stage circuit of an operational amplifier, the operational amplifier, and a signal amplifying method applied to the operational amplifier are provided. The output stage circuit includes an inverting circuit and a compensation module. The inverting circuit is electrically connected to a gain stage circuit of the operational amplifier. The inverting circuit generates an output signal of the operational amplifier. The compensation module includes a first compensation circuit, including a first current providing path and a first suppression activation circuit. The first current providing path provides a first compensation current. The first suppression activation circuit conducts the first compensation current to the inverting circuit if a first compensation condition related to a first gain stage signal generated by the gain stage circuit is satisfied. Variation of the output signal is suppressed because of the first compensation current.

A programmable gain amplifier includes a first gain stage having a first bias current path and a first intermediate node, a second gain stage having a second bias current path and a second intermediate node, a third gain stage having a third bias current path and a third intermediate node, a fourth gain stage having a fourth bias current path and fourth intermediate node, a first resistor coupled between the first intermediate node and the second intermediate node, and a second resistor coupled between the third intermediate node and the fourth intermediate node.

A bi-directional active combiner and splitter using bi-directional variable gain amplifiers (BD_VGAs) is proposed. Advantages of the proposed bi-directional active combiner and splitter includes the following 1) compact sizefor each BD_VGA, cascode transistor pair is small and the same matching network is used by the cascode transistor pair for both directions; 2) high efficiencyno switching loss in signal path, only switched matching; 3) reduced passive trace loss and power consumptionsimplified signal interconnection; 4) active current combiningeliminates large size in the passive combiner; 5) high input-output isolationcascode and neutralization; 6) precise gain control and unequal combining or splittingchanging the gain of the BD_VGA; and 7) phase-invariant amplifier design.

A receiver signal path includes a programmable flat gain stage configured to provide an amplified differential pair of signals based on a first frequency response having a selectable flat gain and a differential input pair of signals received on an input differential pair of nodes. The receiver signal path includes a peaking gain stage configured to generate a second amplified differential pair of signals based on the amplified differential pair of signals according to a second frequency response including a first peak gain at or near a carrier frequency in a first pass band. The first peak gain occurs just prior to a first cutoff frequency of the peaking gain stage. The programmable flat gain stage and the peaking gain stage are configured as a variable peaking gain stage. The selectable flat gain is selectively programmed based on a predetermined power consumption of a receiver path.

An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.

The present invention provides a system and method for operating hybrid concurrent and switched dual-band low noise amplifiers. Embodiments use a concurrent design at the input block of a hybrid LNA to advantageously achieve better impedance matching while using a switch capacitor design at the output block to advantageously achieve a better gain than typical concurrent multiband LNAs. Embodiments might be integrated into wireless devices configured to simultaneously receive on multiple frequency bands while providing gains of 30 dB or more by combining the advantages of concurrent multiband LNAs with the advantages of switched multiband LNAs. In addition to the higher gains provided by embodiments of the hybrid LNA described herein, hybrid multiband LNAs according to embodiments of the present invention provide a smaller device footprint and power requirements than would be required for a receiver including multiple single-band LNAs for amplifying signals for each frequency band individually.

A circuit includes a first transistor having a first control input and first and current terminals. The circuit also includes a second transistor having a second control input and third and fourth current terminals. The third current terminal couples to the first current terminal at a first node. An output stage has a first input, a second input, and an output stage output. The first input couples to the fourth current terminal, and the second input couples to the second current terminal. A resistor has first and second resistor terminals. The first resistor terminal couples to the output stage output, and the second resistor terminal couples to the second control input. A third transistor has a third control input, a fifth current terminal, and a sixth current terminal. The fifth current terminal couples to the first resistor terminal, and the sixth current terminal couples to the second resistor terminal.

An apparatus includes an amplifying circuit configured to include stacked first and second transistors, and to amplify a signal input from an input terminal during an operation in an amplifying mode, and provide the amplified signal to an output terminal, and a negative feedback circuit comprising first to nth sub-negative feedback circuits, each corresponding to a separate gain mode included in the amplifying mode, wherein the negative feedback circuit is configured to provide a variable resistance value to determine a negative feedback gain based on each of the separate gain modes.

A combined resistance circuit 2A includes a first circuitry 20A provided between a first end 2a and a second end 2b. This first circuitry 20A includes a resistor R1 provided between a node N11 and a node N12, a resistor R2 provided between the node N12 and a node N13, a resistor R3 provided between the node N13 and a node N14, a resistor R4 provided between the node N14 and the node N11, a resistor R5 provided between the node N11 and the node N13, a switch SW0 provided in series to the resistor R4 between the node N14 and the node N11, and a switch SW1 provided in series to the resistor R2 between the node N12 and the node N13. The node N12 is connected to the first end and the node N14 is connected to the second end.