A variable gain amplifier includes a pair of amplification and recentering branches. Each branch includes: a resistive element of variable resistance configured to be driven by a variable gain controller; a digitally-driven variable current source configured to be driven by a compensation current driver unit; a first transistor comprising a gate terminal coupled to an input terminal of the variable gain amplifier, and a source terminal coupled to a first terminal of the resistive element; and a second transistor comprising a gate terminal coupled to a drain terminal of the first transistor, and a source terminal coupled to an output terminal of the variable gain amplifier.

A bi-directional active combiner and splitter using bi-directional variable gain amplifiers (BD_VGAs) is proposed. Advantages of the proposed bi-directional active combiner and splitter includes the following 1) compact sizefor each BD_VGA, cascode transistor pair is small and the same matching network is used by the cascode transistor pair for both directions; 2) high efficiencyno switching loss in signal path, only switched matching; 3) reduced passive trace loss and power consumptionsimplified signal interconnection; 4) active current combiningeliminates large size in the passive combiner; 5) high input-output isolationcascode and neutralization; 6) precise gain control and unequal combining or splittingchanging the gain of the BD_VGA; and 7) phase-invariant amplifier design.

Methods and devices addressing design of reconfigurable wideband LNAs to meet stringent gain, noise figure, and linearity requirements with multiple gain modes are disclosed. The disclosed teachings can be used to reconfigure RF receiver front-end to operate in various applications imposing stringent and conflicting requirements, such as 5G NR radios. Wideband and narrowband input and output matching with gain modes using a combination of the same hardware and a switching network are also disclosed.

High-frequency amplifier circuitry includes first amplifier circuitry, second amplifier circuitry, and noise figure improving circuitry. The first amplifier circuitry includes a first transistor and a grounded-gate third transistor. The first transistor has a source grounded via a first source inductor and a gate to which an input signal is applied. The third transistor is configured to output from a drain a signal obtained by amplifying a signal outputted from a drain of the first transistor. The second amplifier circuitry includes a same circuit constant as a circuit constant of the first amplifier circuitry and includes a second transistor and a grounded-gate fourth transistor. The noise figure improving circuitry connects the source of the first transistor and the source of the second transistor to each other.

According to one embodiment, a low noise amplifier (LNA) circuit includes a first stage which includes: a first transistor; a second transistor coupled to the first transistor; a first inductor coupled in between an input port and a gate of the first transistor; and a second inductor coupled to a source of the first transistor, where the first inductor and the second inductor resonates with a gate capacitance of the first transistor for a dual-resonance. The LNA circuit includes a second stage including a third transistor; a fourth transistor coupled between the third transistor and an output port; and a passive network coupled to a gate of the third transistor. The LNA circuit includes a capacitor coupled in between the first and the second stages, where the capacitor transforms an impedance of the passive network to an optimal load for the first amplifier stage.

Systems and methods for amplifying an input signal include amplifier circuitry, an itail connection coupled between a positive voltage circuitry and the negative voltage circuitry and operable to generate an itail voltage corresponding to a greater of the positive voltage input signal (Vp) and the negative voltage input signal (Vn), a first resistor rgp disposed to receive the itail voltage and a first voltage corresponding to Vp, and a second resistor rgn disposed to receive the itail voltage and a second voltage corresponding to Vn. A first current output node is coupled to the output of rgp and operable to output a positive output current (Ioutp) corresponding to the current flowing through rgp, and a second current output is coupled to the output of rgn and operable to output a negative output current (Ioutn) corresponding to the current flowing through rgn.

The invention relates to a gain-control stage (100) for generating gain-control signals (V.sub.c+, V.sub.c) for controlling an external variable-gain amplifying unit (101). The gain-control stage comprises a first (102) and a second differential amplifier unit (112) that receive, at a respective input interface (104,114) a reference voltage signal (V.sub.Ref) and a variable gain-control voltage signal (V.sub.GC). The second differential amplifier unit is configured to provide, via a second output interface (120), a control voltage signal (V.sub.1) to a controllable first current source (106) of the first differential amplifier unit (102). The first differential amplifier unit (102) is configured to provide, via a first output interface (110), the first and the second gain-control signal (V.sub.C+, V.sub.C) in dependence on the variable gain-control voltage signal (V.sub.GC), the reference voltage signal (V.sub.Ref) and a first biasing current (I.sub.B1) that depends on the control voltage signal.

The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode Voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.

Disclosed herein are methods for amplifying a signals. The methods include receiving signals at a plurality of input nodes. The methods also include configuring a gain stage to be in a selected one of a plurality of gain settings, at least some of the gain settings resulting in different impedances presented to the signal. The methods also include adjusting the resistance presented to the signal by the gain stage for the selected gain setting, the adjusted resistance being configured to provide a targeted constant value of the impedance at the input across the plurality of gain settings. The methods also include amplifying at least a portion of the received signals. Adjusting the resistance compensates for changes to the input impedance to improve return loss and mismatch over gain modes.

An RF receiver circuit configuration and design limited by conditions and frequencies to simultaneously provide steady state low-noise signal amplification, frequency down-conversion and image signal rejection. The invention provides combined circuits of an RF transceiver architecture that measure antenna reflected power relative to forward power using the error amplifier signal to adjust the gain of the variable gain amplifier in order to compensate for the mismatch between forward reflected power and forward power at the antenna in order to achieve constant radiated power. The RF receiver circuit may be implemented as one of a CMOS single chip device or as part of an integrated system of CMOS components.