H03G1/0082

PROGRAMMABLE IMPEDANCE NETWORK IN AN AMPLIFIER
20170194923 · 2017-07-06 ·

The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input. A second transistor receives a second input. A plurality of impedance networks is coupled between the first transistor and the second transistor. At least one impedance network of the plurality of impedance networks includes a first impedance path and a second impedance path. The first impedance path is activated during single ended operation, and the second impedance path is activated during differential operation.

METHOD FOR IMPROVING STABLE FREQUENCY RESPONSE OF VARIBLE GAIN AMPLIFIER

A variable gain amplifier having stabilized frequency response for widened gain control range. A resistor-capacitor compensation network is provided between two differential current input ports and corresponding emitter nodes of cross-coupled four transistors in the variable gain amplifier to desensitize the gain control voltages to the system noise and provide compensation to the VGA frequency response when the differential gain control voltage varies the gain setting, yielding a substantially stabilized frequency response over a 3 dB bandwidth ranging from 1 GHz to 60 GHz with a widened gain control range up to 12 dB without increasing power consumption.

VARIABLE GAIN AMPLIFIER AND DRIVER IMPLEMENTING THE SAME
20170117863 · 2017-04-27 ·

A driver that drives an optical device, such as laser diode (LD) and/or optical modulator, is disclosed. The driver includes a variable gain amplifier (VGA) and a post amplifier. The post amplifier amplifies an output of the VGA to a preset amplifier as varying the gain of the VGA. The VGA includes two differential pairs each amplify the input signal oppositely in phases thereof and outputs of the differential pairs are compositely provided to the post amplifier. The gain of the VGA is varied by adjusting contribution of the second differential pair to the output of the VGA.

Method for improving stable frequency response of variable gain amplifier

A variable gain amplifier having stabilized frequency response for widened gain control range. A resistor-capacitor compensation network is provided between two differential current input ports and corresponding emitter nodes of cross-coupled four transistors in the variable gain amplifier to desensitize the gain control voltages to the system noise and provide compensation to the VGA frequency response when the differential gain control voltage varies the gain setting, yielding a substantially stabilized frequency response over a 3 dB bandwidth ranging from 1 GHz to 60 GHz with a widened gain control range up to 12 dB without increasing power consumption.

Differential amplifier

A differential amplifier includes an amplifying stage that outputs an output signal by amplifying an input signal with a gain set by a control signal, and an adjusting stage that stabilizes a DC level of the output signal. The amplifying stage includes a first source supplying a first current, and a load, and determines a ratio of a current flowing through the load to the first current depending on the input signal and the control signal, and generates the output signal from a voltage drop of the load. The adjusting stage includes a second source supplying a second current, and a monitor resistor, and generates a monitor current divided from the second current by the ratio, and duplicates the DC level as a voltage drop of the monitor resistor caused by the monitor current, and controls the first current source and the second current source depending on the DC level.

Programmable impedance network in an amplifier

The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input. A second transistor receives a second input. A plurality of impedance networks is coupled between the first transistor and the second transistor. At least one impedance network of the plurality of impedance networks includes a first impedance path and a second impedance path. The first impedance path is activated during single ended operation, and the second impedance path is activated during differential operation.

ESA phase shifter topology

A phase shifter component is described. Inputs are arranged to selectively receive an inphase component of an in-phase (I) signal or an outphase I signal 180 out of phase with the inphase I signal, and to selectively receive an inphase component of a quadrature-phase (Q) signal or an outphase Q signal 180 out of phase with the inphase Q signal. A first gain portion includes only two transistor elements arranged to amplify the received outphase or inphase I signal. A second gain portion includes only two transistor elements arranged to amplify the received outphase or inphase Q signal. The first and second gain portions are configured to control the gain of the received outphase or inphase I signal and the received outphase or inphase Q signal, respectively, to provide a composite output signal with a desired phase shift between 0 and 360.