The present invention is a system and method for providing a charge detector that utilizes small feedback capacitors in a low-noise, high-gain, system that combines a differential topology in a solid-state amplifier implemented in a complementary metal-oxide semiconductor (CMOS) process with active reset, thereby achieving high dynamic range and robust operations. A custom optoelectronic system is used to measure gain, and while operating at a sampling frequency of 10 kHz, the active reset extends the dynamic range of the charge detector.

A signal amplifying circuit and associated methods and apparatuses, the circuit comprising: a signal path extending from an input terminal to an output terminal, a gain controller arranged to control the gain applied along the signal path in response to a control signal; an output stage within the signal path for generating the output signal, the output stage having a gain that is substantially independent of its supply voltage, and a variable voltage power supply comprising a charge pump for providing positive and negative output voltages, the charge pump comprising a network of switches that is operable in a number of different states and a controller for operating the switches in a sequence of the states so as to generate positive and negative output voltages together spanning a voltage approximately equal to the input voltage.

A signal amplifying circuit and associated methods and apparatuses, the circuit comprising: a signal path extending from an input terminal to an output terminal, a gain controller arranged to control the gain applied along the signal path in response to a control signal; an output stage within the signal path for generating the output signal, the output stage having a gain that is substantially independent of its supply voltage, and a variable voltage power supply comprising a charge pump for providing positive and negative output voltages, the charge pump comprising a network of switches that is operable in a number of different states and a controller for operating the switches in a sequence of the states so as to generate positive and negative output voltages together spanning a voltage approximately equal to the input voltage.

The present invention is a system and method for providing a charge detector that utilizes small feedback capacitors in a low-noise, high-gain, system that combines a differential topology in a solid-state amplifier implemented in a complementary metal-oxide semiconductor (CMOS) process with active reset, thereby achieving high dynamic range and robust operations. A custom optoelectronic system is used to measure gain, and while operating at a sampling frequency of 10 kHz, the active reset extends the dynamic range of the charge detector.

A method for operating a charge pump having a variable switching frequency may include comparing a target minimum output voltage with an output voltage generated at an output of the charge pump and controlling switching of switches of the charge pump based on the comparison such that the variable switching frequency varies as an output current driven by the charge pump varies.

A switchable amplifier and comparator circuit includes an operational amplifier having an inverting input, a non-inverting input, a first differential output and a second differential output, the first differential output switchably coupled to the inverting input and the second differential output switchably coupled to the non-inverting input. A first feedback capacitor is coupled to the inverting input and switchably coupled to the first differential output, a second feedback capacitor is coupled to the non-inverting input and switchably coupled to the second differential output. A capacitive load is switchably coupled between the first differential output and the second differential output. A diode clamp circuit is switchably coupled between the first differential output and the second differential output. A resistive load is switchably coupled between the first differential output and the second differential output.

An apparatus comprises a plurality of selectable gain stages connected in parallel between a first bias voltage and ground, wherein each selectable gain stage comprises an amplification portion and a current steering portion, and wherein the current steering portion comprises a first selectable signal path connected between an output of the amplification portion and a signal output terminal, and a second selectable signal path connected between the output of the amplification portion and ground through a shunt device.

An I-V conversion module includes: a current output type sensor, a pre-integral circuit, a charge transfer auxiliary circuit, and an I-V transformation circuit including an inverting amplifier. The current output type sensor is connected to an input end of the I-V transformation circuit through the pre-integral circuit. The charge transfer auxiliary circuit connects in parallel with the inverting amplifier. When both the pre-integral circuit and the charge transfer auxiliary circuit are open circuits, the pre-integral circuit pre-integrates the induction current output by the current output type sensor to store pre-integral charges. When both pre-integral circuit and the charge transfer auxiliary circuit are closed circuits, the pre-integral charges are transferred to the I-V transformation circuit. In these embodiments, both the time for establishing the I-V conversion module and power consumption can be reduced.

An electronic circuit comprises an input stage, a gain stage operatively coupled to the input stage, a primary output stage operatively coupled to the gain stage, a replica output stage operatively coupled to the gain stage in parallel to the primary output stage, and a clock circuit. The clock circuit operates the electronic circuit in multiple phases including a sampling phase to disconnect the primary output stage and the replica output stage from the gain stage to obtain an offset voltage, an active phase to reconnect the primary output stage to apply the offset voltage to reduce an offset at the primary output stage, and an intermediate phase to first reconnect the replica output stage to the gain stage prior to the active phase.

A semiconductor circuit including a clocked comparator and an offset application circuit. The clocked comparator is configured to receive a first input signal and a second input signal from a host and compare the first input signal and the second input signal. The offset application circuit is configured to apply an offset to the first input signal. The clocked comparator is configured to be driven based on a reference clock provided from the host.