A switched-capacitor gain stage circuit and method include an amplifier connected to an input sampling circuit with sampling switched capacitors for coupling an input voltage and a first or second reference voltage to one or more central nodes during a sampling phase and for coupling the one or more central nodes to an amplifier input during a gain phase, wherein a reference loading circuit uses a plurality of sampling switched capacitors connected in a switching configuration to selectively couple a first reference voltage and/or a second reference voltage to the central node by pre-charging the plurality of sampling switched capacitors with the first and second reference voltages during the sampling phase, and by coupling each of the first and second reference voltages to at least one of the plurality of sampling switched capacitors when connected to the central node during the gain phase.

A power amplification module includes a first input terminal that receives a first transmit signal in a first frequency band, a second input terminal that receives a second transmit signal in a second frequency band having a narrower transmit/receive frequency interval than the first frequency band, a first amplification circuit that receives and amplifies the first transmit signal to produce a first amplified signal and outputs the first amplified signal, a second amplification circuit that receives and amplifies the second transmit signal to produce a second amplified signal and outputs the second amplified signal, a third amplification circuit that receives and amplifies the first or second amplified signal to produce an output signal and outputs the output signal, and an attenuation circuit located between the second input terminal and the second amplification circuit and configured to attenuate a receive frequency band component of the second frequency band.

A variable gain amplifier circuit including a first amplifier, a second amplifier, and a variable capacitor connected in series between the first amplifier and the second amplifier is disclosed. As a gain of the variable gain amplifier circuit varies, the input impedance, output impedance, noise figure and third-order output intercept point (OIP3) of the variable gain amplifier circuit remain unchanged.

Various embodiments of the present technology may provide methods and apparatus for a track-and-hold amplifier configured to sample and amplify an analog signal. Methods and apparatus for a track-and-hold amplifier according to various aspects of the present invention may provide an isolation circuit configured to isolate transient current in a track-and-hold capacitor during a track phase. According to various embodiments, selective activation of the isolation circuit provides a settling time that is independent of the gain of the amplifier.

An attenuator for attenuating a signal is disclosed. The attenuator comprises a differential input port with a positive input node and a negative input node to receive the signal; and a differential output port with a positive output node and a negative output node to output the attenuated signal. The attenuator further comprises a first switched resistor network connected between the positive input node and the positive output node; and a second switched resistor network connected between the negative input node and the negative output node. Further a pair of compensation paths is connected to the first and second switched resistor networks for cancellation their parasitic leakages, where a first compensation path is connected between the positive input node and the negative output node, and a second compensation path is connected between the negative input node and the positive output node. The attenuator further comprises a control circuit to generate control signals for controlling the first and second switched resistor networks.

A semiconductor circuit including a clocked comparator and an offset application circuit. The clocked comparator is configured to receive a first input signal and a second input signal from a host and compare the first input signal and the second input signal. The offset application circuit is configured to apply an offset to the first input signal. The clocked comparator is configured to be driven based on a reference clock provided from the host.

A variable gain amplifier circuit including a first amplifier, a second amplifier, and a variable capacitor connected in series between the first amplifier and the second amplifier is disclosed. As a gain of the variable gain amplifier circuit varies, the input impedance, output impedance, noise figure and third-order output intercept point (OIP3) of the variable gain amplifier circuit remain unchanged.

Processes and systems for producing glass fibers having regions devoid of glass using submerged combustion melters, including feeding a vitrifiable feed material into a feed inlet of a melting zone of a melter vessel, and heating the vitrifiable material with at least one burner directing combustion products of an oxidant and a first fuel into the melting zone under a level of the molten material in the zone. One or more of the burners is configured to impart heat and turbulence to the molten material, producing a turbulent molten material comprising a plurality of bubbles suspended in the molten material, the bubbles comprising at least some of the combustion products, and optionally other gas species introduced by the burners. The molten material and bubbles are drawn through a bushing fluidly connected to a forehearth to produce a glass fiber comprising a plurality of interior regions substantially devoid of glass.

An attenuator for attenuating a signal is disclosed. The attenuator comprises a differential input port with a positive input node and a negative input node to receive the signal; and a differential output port with a positive output node and a negative output node to output the attenuated signal. The attenuator further comprises a first switched resistor network connected between the positive input node and the positive output node; and a second switched resistor network connected between the negative input node and the negative output node. Further a pair of compensation paths is connected to the first and second switched resistor networks for cancellation their parasitic leakages, where a first compensation path is connected between the positive input node and the negative output node, and a second compensation path is connected between the negative input node and the positive output node. The attenuator further comprises a control circuit to generate control signals for controlling the first and second switched resistor networks.

An RF transceiver front-end circuit includes an antenna, a first transceiving switch, a reception processing unit, a transmission processing unit and a transmission unit. The reception processing unit includes a low-noise amplifier, a first variable gain amplifier at a back-end circuit of the low-noise amplifier, and a first phase shifter at a back-end circuit of the first variable gain amplifier, wherein a phase of the first variable gain amplifier is constant. The transmission processing unit includes a power amplifier, a second phase shifter at a front-end circuit of the power amplifier, and a second variable gain amplifier at a front-end circuit of the second phase shifter, wherein a phase of the second variable gain amplifier is constant. The transmission unit includes a transmission line and a plurality of passive phase adjustors controlled to change a phase shifting angle of a signal on the transmission line.