Systems, devices, and methods for determining and establishing frequency-dependent gain compensation in wide bandwidth communication systems are disclosed. Variable frequency-dependent gain compensation circuits, or variable equalizers, have settings that configure them to establish discrete frequency-dependent gain compensation. The frequency-dependent gain compensation can include various types and levels of gain slope and/or ripple. The settings of the variable equalizers can be set by control signals established a control circuit in response to signals from an external computer. The variable equalizers are coupled to other circuits or devices and the frequency-dependent gain of the combined circuit are measured. The settings of the variable equalizer are then changed to establish an optimal frequency-dependent gain profile or frequency-dependent gain that is closest to a predetermined frequency-dependent target gain profile. The settings can then be saved in a memory or register.

A receiver circuit receives a signal from a semiconductor device. The receiver circuit includes an input buffer including a first plurality of transistors, the input buffer being configured to detect a fabrication condition of the receiver circuit, generate a control signal according to the detected fabrication condition, and control a gain of an input signal by adjusting a number of operating transistors among the first plurality of transistors in response to the control signal; and a latch circuit configured to latch an output signal of the input buffer, and adjust threshold voltages of a second plurality of transistors in response to a test signal.

A variable gain amplifier includes a pair of amplification and recentering branches. Each branch includes: a resistive element of variable resistance configured to be driven by a variable gain controller; a digitally-driven variable current source configured to be driven by a compensation current driver unit; a first transistor comprising a gate terminal coupled to an input terminal of the variable gain amplifier, and a source terminal coupled to a first terminal of the resistive element; and a second transistor comprising a gate terminal coupled to a drain terminal of the first transistor, and a source terminal coupled to an output terminal of the variable gain amplifier.

Methods and systems for optimizing amplifier operations are described. The described methods and systems particularly describe a feed-forward control circuit that may also be used as a feed-back control circuit in certain applications. The feed-forward control circuit provides a control signal that may be used to configure an amplifier in a variety of ways.

An apparatus including an electronic circuit. The apparatus includes a path unit configured to form a first impedance for controlling a gain of an input signal. The apparatus also includes a shunt unit configured to form a second impedance for performing attenuation between the path unit and a ground, wherein the path unit forms the first impedance using an on-resistance of at least one transistor.

A low noise amplifier has integral noise cancellation to provide a low noise figure and operation over a frequency range of 0.5 GHz-50 GHz. An amplifier amplifies an input signal as well as noise present with the amplified signal and amplified noise being out of phase and in phase, respectively, with the corresponding inputs. A feedback circuit that is non-linear with frequency enables a constant amplification. A summation circuit combines amplified signals with the noise being cancelled since two combined noise signals being summed are 180 degrees out of phase to each other. An optional secondary amplification stage provides additional amplification. Preferably, the amplifier, auxiliary amplifier and the summation device utilize CMOS transistors disposed on an SOI substrate with impedance stabilization over the frequency range.

Methods and systems for phased array tapering include setting a gain at a phase-invariant variable gain amplifier in each of a set of front-ends of a phased array transceiver, to perform tapering of beam pattern side lobes. Setting the gain includes setting a first gain at a first stage of the phase-invariant variable gain amplifier and setting a second gain at a second stage of the phase-invariant variable gain amplifier. A dependency of a phase shift of the first stage on the gain of the first stage is equal to and opposite a dependency of a phase shift of the second stage on the gain of the second stage.

The disclosure relates to technology for power supply for a voltage controller oscillator (VCO), where the power supply has a closed loop mode and an open loop mode. In closed loop mode, a peak detector circuit determines the amplitude of the output for the VCO, which is compared to a reference value in an automatic gain control loop. An input voltage for the VCO is determined based on a difference between the reference value and the output of the peak detector circuit. The peak detector circuit can be implemented using parasitic bipolar devices in an integrated circuit formed in a CMOS process. While operating in the closed loop mode, a controller monitors the input voltage and, when the input voltage is stabilized, the controller uses this input voltage value determined in open loop mode.

Disclosed herein are methods for amplifying a signals. The methods include receiving signals at a plurality of input nodes. The methods also include configuring a gain stage to be in a selected one of a plurality of gain settings, at least some of the gain settings resulting in different impedances presented to the signal. The methods also include adjusting the resistance presented to the signal by the gain stage for the selected gain setting, the adjusted resistance being configured to provide a targeted constant value of the impedance at the input across the plurality of gain settings. The methods also include amplifying at least a portion of the received signals. Adjusting the resistance compensates for changes to the input impedance to improve return loss and mismatch over gain modes.

The disclosure relates to technology for power supply for a voltage controller oscillator (VCO). A peak detector circuit determines the amplitude of the output for the VCO, which is compared to a reference value in an automatic gain control loop. An input voltage for the VCO is determined based on a difference between the reference value and the output of the peak detector circuit. The peak detector circuit can be implemented using parasitic bipolar devices in an integrated circuit formed in a CMOS process.