Patent classifications
H03G3/3036
TRANSIMPEDANCE AMPLIFIER CIRCUIT
A transimpedance amplifier circuit includes an amplifier circuit that converts a current signal into a voltage signal with a gain being varied based on a control signal and a gain control circuit that generates the control signal based on an amplitude of the voltage signal. The gain control circuit includes a detection circuit that generates an amplitude-detection-signal in accordance with the amplitude of the voltage signal, a setting circuit that generates an amplitude-reference-signal, a differential voltage generation circuit that generates a differential-voltage-signal obtained by offsetting a voltage difference between the amplitude-detection-signal and the amplitude-reference-signal based on an amplitude-setting-signal, an operational transconductance amplifier (OTA) that generates a differential-current-signal based on the differential-voltage-signal, and a variable capacitor circuit having a variable capacitance being varied based on the amplitude-setting-signal, and configured to be charged/discharged by the differential-current-signal and output a charging voltage. The control signal is generated based on the charging voltage.
APPARATUS FOR DETERMINING WHEN AN AUTOMATIC GAIN CONTROL CIRCUIT HAS SETTLED
In one embodiment, an apparatus includes: a low noise amplifier (LNA) to receive and amplify a radio frequency (RF) signal, the LNA having a first controllable gain; a mixer to downconvert the RF signal to a second frequency signal; a programmable gain amplifier (PGA) coupled to the mixer to amplify the second frequency signal, the PGA having a second controllable gain; a digitizer to digitize the second frequency signal to a digitized signal; a demodulator coupled to the digitizer to demodulate the digitized signal; an automatic gain control (AGC) circuit to control one or more of the first controllable gain and the second controllable gain; and an AGC settling circuit to cause the demodulator to begin operation in response to determining that the AGC circuit has settled.
RADIO FREQUENCY FRONT END WITH INTEGRATED CHANNEL MATCHING CALIBRATION
Radio frequency (RF) front ends with integrated channel matching calibration are provided herein. In one aspect, a front end system includes: a plurality of front end amplification chains including transmit and receive chains for at least two radio frequency bands, each of the front end amplification chains configured to either transmit or receive radio frequency signals via one of a plurality of antennas, and each of the front end amplification chains includes an amplifier configured to receive a bias current and amplify the corresponding radio frequency signal based on the bias current, a control circuit configured to generate each of the bias currents, and a multiplexor configured to receive the bias currents and provide the bias currents to the corresponding amplifiers.
Power Amplifier Self-Heating Compensation Circuit
Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain “droop” due to self-heating using a Sample and Hold (S&H) circuit. The S&H circuit samples and holds an initial temperature of the PA at commencement of a pulse. Thereafter, the S&H circuit generates a continuous measurement that corresponds to the temperature of the PA during the remainder of the pulse. A Gain Control signal is generated that is a function of the difference between the initial temperature and the operating temperature of the PA as the PA self-heats for the duration of the pulse. The Gain Control signal is applied to one or more adjustable or tunable circuits within a PA to offset the Gain droop of the PA.
Amplifier Circuitry with Gain Adjustments and Input Matching
An electronic device may include wireless circuitry with processor circuitry, a transceiver circuit, a front-end module, and an antenna. The front-end module may include amplifier circuitry such as low noise amplifier circuitry for amplifying received radio-frequency signals. The amplifier circuitry may include an amplifier having an input and an output, an adjustable load component coupled to the input, and an adjustable feedback component coupled across the input and output. A control circuit may simultaneously adjust the load and feedback components to tune the gain of the amplifier circuitry while maintaining the input resistance at a desired target level. The load and feedback components can be the same or different types of adjustable passive components.
Q-BAND BLOCK DOWN CONVERTER
In some implementations, a radiofrequency down converter comprises an input port to receive a radiofrequency input signal, and the down converter includes a first bandpass filter configured to filter the input signal. The down converter includes a mixer stage coupled to the bandpass filter, the mixer stage being configured to generate a mixer output signal by processing the filtered input signal using a gain adjustment device, one or more amplifiers, and a mixer. The down converter includes a signal adjustment stage coupled to receive the mixer output signal, the signal adjustment stage comprising: a temperature compensation device configured to compensate for changes in signal gain due to changes in temperature; a second bandpass filter; a gain adjustment device; one or more amplifiers; and a low pass filter. The down converter comprises an output port coupled to output an adjusted mixer output signal from the signal adjustment stage.
Receiving circuit, and semiconductor apparatus and semiconductor system using the same
A receiving circuit may include a first amplifying circuit, a second amplifying circuit, a third amplifying circuit, and a feedback circuit. The first amplifying circuit amplifies a first input signal and a second input signal to generate a first amplified signal and a second amplified signal, respectively. The second amplifying circuit amplifies the first amplified signal and the second amplified signal to generate a first preliminary output signal and a second preliminary output signal, respectively. The third amplifying circuit amplifies the first preliminary output signal and the second preliminary output signal to generate a first output signal and a second output signal, respectively. The feedback circuit changes voltage levels of the first amplified signal and the second amplified signal based on a current control signal, the first output signal, and the second output signal.
Gain adjustment circuit
A gain adjustment circuit is coupled with a transmitting device and a receiving device that are in proximity to each other. The gain adjustment circuit receives a baseband signal that is generated based on gain signals and a power associated with a reception of a data packet by the receiving device. The gain adjustment circuit further receives previous transmission information of the transmitting device. The gain adjustment circuit predicts a time of transmission of a control packet from the transmitting device and determines whether the time of transmission overlaps with a time period of reception of the data packet by the receiving device. The gain adjustment circuit further generates and provides gain signals to the receiving device such that a signal interference during the transmission of the control packet and the reception of the data packet is mitigated.
Power supply for voltage controlled oscillators with automatic gain control
The disclosure relates to technology for power supply for a voltage controller oscillator (VCO). A peak detector circuit determines the amplitude of the output for the VCO, which is compared to a reference value in an automatic gain control loop. An input voltage for the VCO is determined based on a difference between the reference value and the output of the peak detector circuit. The peak detector circuit can be implemented using parasitic bipolar devices in an integrated circuit formed in a CMOS process.
RF PEAK DETECTOR CIRCUIT
An apparatus comprises a transistor pair including a first metal oxide semiconductor field effect transistor (MOSFET) coupled to a second MOSFET. The first MOSFET includes a first gate terminal and a first drain terminal. The second MOSFET comprises a second gate terminal and a second drain terminal. The first gate terminal is configured to receive a first signal. The second gate terminal is configured to receive a second signal that is phase shifted with respect to the first signal. An output node is coupled to the first drain terminal and the second drain terminal and configured to output a third signal that is proportional to a power of the first signal and the second signal.