The disclosure relates to technology for power supply for a voltage controller oscillator (VCO), where the power supply has a closed loop mode and an open loop mode. In closed loop mode, a peak detector circuit determines the amplitude of the output for the VCO, which is compared to a reference value in an automatic gain control loop. An input voltage for the VCO is determined based on a difference between the reference value and the output of the peak detector circuit. The peak detector circuit can be implemented using parasitic bipolar devices in an integrated circuit formed in a CMOS process. While operating in the closed loop mode, a controller monitors the input voltage and, when the input voltage is stabilized, the controller uses this input voltage value determined in open loop mode.

The disclosure relates to technology for power supply for a voltage controller oscillator (VCO). A peak detector circuit determines the amplitude of the output for the VCO, which is compared to a reference value in an automatic gain control loop. An input voltage for the VCO is determined based on a difference between the reference value and the output of the peak detector circuit. The peak detector circuit can be implemented using parasitic bipolar devices in an integrated circuit formed in a CMOS process.

In an operating method of a radio frequency integrated circuit (RFIC) including a transmission circuit and a reception circuit, the operating method includes receiving, from a modem, first information for setting transmission power of the transmission circuit or second information about a blocker which is a frequency signal unused by the RFIC, obtaining an allowable value of phase noise of a local oscillator included in the transmission circuit, using the first information, obtaining an allowable value of phase noise of a local oscillator included in the reception circuit, using the second information, determining a level of a driving voltage, using the obtained allowable values of the phase noises, and providing the driving voltage to the local oscillators.

The disclosed technology is related to a radio-frequency (RF) amplifier having a bypass circuit and a resonant structure to improve performance in a bypass mode (e.g., a low gain mode). The disclosed amplifiers have a resonant structure that effectively isolates an amplifier core from a bypass circuit. For example, in a bypass mode, the resonant structure is configured to create an open impedance looking into the amplifier core input. This effectively removes any loading from the amplifier core to the bypass circuit. The disclosed amplifiers with resonant structures improve linearity performance in bypass modes due at least in part to the open impedance to the amplifier core provided by the resonant structure.

A power stage includes a power stage amplifier, selectable matching networks, and phase-change material (PCM) radio frequency (RF) switches. Each of the PCM RF switches includes a heating element transverse to a PCM, the heating element approximately defining an active segment of the PCM. A power stage amplifier output is connected to the PCM RF switches. Each of the PCM RF switches is connected to one of the selectable matching networks. A power stage amplifier output is coupled to or decoupled from one of the selectable matching networks by one of the PCM RF switches. In one approach, the power stage is included in a power amplifier module of a communications device. The power amplifier module further includes a bias and match controller that biases the power stage amplifier, and that uses one of the PCM RF switches to couple or decouple the power stage amplifier output.

An apparatus for detecting a neural spike includes: a preprocessing circuit configured to remove a low-frequency component from a neural signal to form a low-frequency component removed neural signal, and amplify the low-frequency component removed neural signal; a comparing circuit configured to compare an output signal of the preprocessing circuit to a threshold signal; a merging circuit configured to merge spikes within a reference interval of an output signal of the comparing circuit into one peak, and to generate, based on the merging of the spikes, an output signal comprising pulses; and a counting circuit configured to count the pulses.

Circuits comprising: digital-to-amplitude converter (DAC), comprising: binary weighted switching transistors (BWSTs), each having gate coupled to amplitude control bit ACB, and wherein the drain of each of the BWSTs are connected together and wherein the source of each of the BWSTs are connected together; transistor M1 having gate coupled to input signal and first bias voltage BV1 and source coupled to the drains of the BWSTs; transistor M2 having gate coupled to BV2 and source coupled to the drain of M1; transistor M3 having gate coupled to BV3 and source coupled to the drain of M2; transistor having gate coupled to BV4, source coupled to the drain of M3; and inverter having input coupled to another ACB and having output coupled to the output of the DAC and the drain of M4.

An envelope tracking (ET) amplifier circuit is provided. The ET amplifier circuit includes an amplifier circuit configured to amplify a radio frequency (RF) signal based on an ET modulated voltage. The ET modulated voltage corresponds to a time-variant voltage envelope, which can be misaligned from a time-variant signal envelope of the RF signal due to inherent temporal delay in the ET amplifier circuit. As a result, the amplifier circuit may suffer degraded linearity performance. In this regard, a voltage processing circuit is provided in the ET amplifier circuit and configured to operate in a low-bandwidth mode and a high-bandwidth mode. In the high-bandwidth mode, the voltage processing circuit is configured to cause the ET modulated voltage to be modified to help improve delay tolerance of the ET amplifier circuit. As a result, it may be possible to reduce linearity degradation of the amplifier circuit to a predetermined threshold.

A communications receiver with improved blocker performance including multiple gain tables selected based on a number of reductions or back offs from a maximum coarse gain setting. A receiver chain with multiple gain stages converts a received signal to a digital format, determines the power level of the received signal, and provides an overload indication. A first gain table maximizes SNR and SNDR for weak blockers and at least one additional gain table successively improves SNDR for stronger blockers. An AGC circuit initially sets the coarse gain setting to maximum, and backs off a number of coarse gain steps until the receiver chain is not overloaded. The number of back off steps is used to select a gain table, the power level is used to select an entry in the selected table, and the selected entry includes gain settings for the gain stages of the receiver chain.

Provided are n antennas and n power change units; a power control unit; a power change management unit managing a common power change amount and an individual power change amount; a common power notification unit notifying the power control unit of the common power change amount in accordance with a target terminal; an individual power notification unit notifying the power control unit in advance of the individual power change amount in accordance with the each terminal at a prescribed timing, in which the power control unit stores the individual power change amount in a storage unit, and performs control of power changing by adding up the common power change amount in accordance with the target terminal, which is notified from the common power notification unit, and the individual power change amount.