An RF receiver circuit configuration and design is limited by conditions and frequencies to simultaneously provide steady state low-noise signal amplification, frequency down-conversion, and image signal rejection. The RF receiver circuit may be implemented as one of a CMOS single chip device or as part of an integrated system of CMOS components.

An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.

An apparatus includes a first half-cell, a second half cell and a multiplexer. The first half-cell may comprise a first input stage configured to present a first input signal to a first auto-zero stage. The second half-cell may comprise a second input stage configured to present a second input signal to a second auto-zero stage. The multiplexer may receive a first output from the first auto-zero stage, receive a second output from the second auto-zero stage and present one of the first output and the second output. The first half-cell and the second half-cell may implement a capacitive coupling. The capacitive coupling may provide a rail-to-rail common-mode input range. The first half-cell and the second half-cell may prevent a mismatch between data signals and clock signals. The first half-cell and the second half-cell may each be configured to implement a calibration when idle.

The invention relates to an amplification circuit (100), comprising: a VGA (2), an AGC loop (10) for automatically controlling the gain of the VGA (2), a switching circuit (14) for switching between an AGC mode, in which the gain of the VGA (2) is automatically controlled by an output signal of the AGC loop (10) and a manual gain control, MGC, mode, in which the gain of the VGA (2) can be manually controlled by an input signal, and a read/write circuit (30) with a contact (31) for connection to a peripheral system, wherein the read/write circuit (30) is configured, in the MGC mode, to provide the input signal from the contact (31) via a write-mode path (32) to the VGA (2), and, in the AGC mode, to provide the output signal of the AGC loop (10) via a read-mode path (33) on the contact (31).

A wireless communications system having at least one RIM associated with a remote unit. The RIMs and the remote units (RU) are configured for transmitting and receiving test signal over at least one narrow band of frequencies. The system includes a plurality of signal generators associated with a signal path, each signal generator configured for generating a test signal over the at least one narrow band of frequencies; a controller configured to generate a test signal for the signal path; and, an equalizer for adjusting gain for the signal path according to at least one of the narrow band of frequencies.

Systems and methods providing a wakeup receiver for latency-critical applications are described herein. An example system includes a wakeup receiver communicatively coupled to a communication channel. The wakeup receiver is configured to monitor an input signal of the communication channel and down-convert the input signal to a DC signal. The system also includes an analog to digital converter (ADC) configured to digitize the DC signal and provide an ADC output. The system further includes a digital baseband (DBB) module configured to determine a received signal strength indication (RSSI) from the signal. The DBB is also configured to, for each packet, determine a respective packet length and compare the RSSI and respective packet length with a two-dimensional template. The DBB is additionally configured to, based on the comparison, determine an interrupt condition and, based on determining the interrupt condition, generate a wakeup signal.

An electronic device for receiving a radio signal includes an upstream amplifier configured to amplify a received radio signal, a control module configured to control a gain of the upstream amplifier, and a mixer connected at the output of the upstream amplifier and configured to mix the signal from the upstream amplifier with a reference signal. The control module is further configured to perform an intermodulation detection, by commanding the generation by the upstream amplifier of a gain increase and comparing a first power with a second power, the first and second powers being respective powers of a signal at the output of the mixer, the first power being measured in the absence of gain increase and the second power being measured in the presence of the gain increase.

A system and a method for calibrating an output signal of an antenna is disclosed. In one aspect, an apparatus includes a first digital adder configured to generate a gain offset by at least adding gain calibration data from non-volatile memory and gain command data from static memory. The apparatus further includes an amplitude gain circuit configured to modify, based at least in part on the gain offset, an amplitude of a first output signal of a first antenna. The modified amplitude of the first output signal is provided to enable pre-calibration of the first output signal. The apparatus further includes a power detector configured to measure an output power of the first output signal. The apparatus further includes at least one processor configured to generate a difference between the measured and expected output power, and adjust gain command data in response to the generated difference.

A multi-gain LNA with inductive source degeneration is presented. The inductive source degeneration is provided via a tunable degeneration network that includes an inductor in parallel with one or more switchable shunting networks. Each shunting network includes a shunting capacitor that can selectively be coupled in parallel to the inductor. A capacitance of the shunting capacitor is calculated so that a combined impedance of the inductor and the shunting capacitor at a narrowband frequency of operation is effectively an inductance. The inductance is calculated according to a desired gain of the LNA. According to one aspect, the switchable shunting network includes a resistor in series connection with the shunting capacitor to provide broadband frequency response stability of the tunable degeneration network. According to another aspect, the LNA includes a plurality of selectable branches to further control gain of the LNA.

An automatic gain control circuit controls a gain of a wireless receiver in accordance with an amplitude of a reception signal. The automatic gain control circuit includes a reference level calculator, a register, a reference level adjuster, and a bit width conversion circuit. The reference level calculator calculates a reference level on the basis of the amplitude of the reception signal. The register stores an adjustment value. The reference level adjuster adjusts the reference level on the basis of the adjustment value stored in the register. The bit width conversion circuit performs a bit width conversion for the entire amplitude direction by changing a bit pitch for determining discrete data values of the reception signal, on the basis of the adjusted reference level.