H03G3/3052

LOWER POWER AUTO-ZEROING RECEIVER INCORPORATING CTLE, VGA, AND DFE
20190296691 · 2019-09-26 ·

An apparatus includes a first half-cell, a second half cell and a multiplexer. The first half-cell may comprise a first input stage configured to present a first input signal to a first auto-zero stage. The second half-cell may comprise a second input stage configured to present a second input signal to a second auto-zero stage. The multiplexer may receive a first output from the first auto-zero stage, receive a second output from the second auto-zero stage and present one of the first output and the second output. The first half-cell and the second half-cell may implement a capacitive coupling. The capacitive coupling may provide a rail-to-rail common-mode input range. The first half-cell and the second half-cell may prevent a mismatch between data signals and clock signals. The first half-cell and the second half-cell may each be configured to implement a calibration when idle.

Fast settling peak detector
10425071 · 2019-09-24 · ·

The present disclosure describes aspects of a fast settling peak detector. In some aspects, a peak detector circuit includes a first transistor having a gate coupled to an input of the circuit at which a signal is received and a drain coupled to a source of a second transistor. Current may flow in the first and second transistors responsive to the signal. The circuit also includes a third transistor having a gate coupled, via a signal-inverting component, to the input of the circuit and a drain coupled to a source of a fourth transistor. Through an inversion of the signal, other current flowing in the third and fourth transistor can reduce or cancel a frequency component of the current in the first and second transistors. In some cases, this precludes a need to filter the frequency component from an output of the circuit.

Automatic gain compression detection and gain control for analog front-end with nonlinear distortion

Methods and systems are provided for gain control in circuits. Gain applied in a circuit may be set to a baseline set gain. A first baseline parameter, associated with a first feature of a particular pattern of a signal at said baseline set gain, and a second baseline parameter, associated with a second feature of said particular pattern of the signal at said baseline set gain, may be determined. The gain is then set a current set gain, and a gain compression ratio may be determined based on one or more of said first baseline parameter, said second baseline parameter, a first current parameter associated with said first feature of at said current set gain, and a second current parameter associated with said second feature at said current set gain. Said current set gain may then be adjusted until said gain compression ratio reaches a predefined limit.

Broadband image-reject receiver for multi-band millimeter-wave 5G communication

According to one embodiment, a radio frequency (RF) receiver circuit includes a low noise amplifier, a poly-phase filter, and an in-phase quadrature (IQ) mixer circuit coupled between the low noise amplifier and the poly-phase filter. The IQ mixer circuit includes an IQ generator having a differential in-phase input port, a differential in-phase output port, and a differential quadrature output port; a first frequency mixer having a differential local oscillator (LO) input port, where the differential LO input port of the first frequency mixer are coupled to the differential in-phase output port of the IQ generator to drive the first frequency mixer; and a second frequency mixer having a differential LO port, where the differential LO input port of the second frequency mixer are coupled to the differential quadrature output port of the IQ generator to drive the second frequency mixer.

FILTERING TECHNIQUES

In some embodiments, a filtering technique can include a pre-amplifier filter configured to filter a signal, and an amplifier assembly configured to amplify the filtered signal. The filtering technique can further include a filter circuit configured to provide selective filtering of the amplified signal based at least in part on a rejection level of the pre-amplifier filter and a gain of the amplifier assembly.

Multiplexed RFAGC for frequency diversity receivers

The present invention concerns a system for controlling gain when time-sharing a tuner in a frequency diversity receiver. Two radio-frequency automatic gain control (RFAGC) filter capacitors are used, each capacitor corresponding to one of the currently utilized frequencies in the frequency diversity scheme. The capacitors are switched in tandem with the tuner frequency selection. This allows the capacitor associated with a tuned frequency to retain the RFAGC voltage until the tuner returns to that frequency.

Tunable Effective Inductance for Multi-Gain LNA with Inductive Source Degeneration
20240171145 · 2024-05-23 ·

A multi-gain LNA with inductive source degeneration is presented. The inductive source degeneration is provided via a tunable degeneration network that includes an inductor in parallel with one or more switchable shunting networks. Each shunting network includes a shunting capacitor that can selectively be coupled in parallel to the inductor. A capacitance of the shunting capacitor is calculated so that a combined impedance of the inductor and the shunting capacitor at a narrowband frequency of operation is effectively an inductance. The inductance is calculated according to a desired gain of the LNA. According to one aspect, the switchable shunting network includes a resistor in series connection with the shunting capacitor to provide broadband frequency response stability of the tunable degeneration network. According to another aspect, the LNA includes a plurality of selectable branches to further control gain of the LNA.

Selectively activating oscillation modules based on signal strengths

At least some embodiments are directed to a receiver system that comprises a first oscillation module configured to provide oscillating signals of differing frequencies and a second oscillation module configured to provide other oscillating signals of the differing frequencies. The second oscillation module is configured to produce less noise than the first oscillation module. A controller is coupled to the first and second oscillation modules and configured to selectively activate and deactivate each of the first and second oscillation modules based on signal strengths of primary signals received via a wireless medium and based on signal strengths of interference signals received via the wireless medium.

Circuit arrangement for compensating for signal attenuation during the transmission of signals from or to a mobile communications device, and associated method
10368326 · 2019-07-30 · ·

A circuit arrangement for compensating for signal attenuation during the transmission of transmission signals of a mobile communications device includes at least one amplifier is switched out of the signal transmission path or is deenergized, or does not amplify, attenuate or forward the detected input signal, unless an input signal level is detected which is greater than or equal to the input signal detection level (S.sub.EP) or a trigger level (S.sub.AP) which is at most 10 dB higher than the same. Alternatively or in combination, the amplifier is operated at a variable amplification factor in an adjustment range (X1) which begins at an input signal detection level (S.sub.EP) or a trigger level (S.sub.AP) which is at most 10 dB higher than the same, and extends to cover higher signal levels than these, wherein, if the input signal detection level (S.sub.EP) or the trigger level (S.sub.AP) is reached or exceeded, the input signal is either non-amplified or is attenuated at an amplification factor?1.

Hybrid variable gain amplifier

Hybrid variable gain amplifiers and methods of controlling hybrid VGAs are disclosed. The hybrid VGA includes a first portion that provides a current path between a positive input and a positive output, and a current path either between the positive input and a negative output, in a first mode of operation, or between the positive input and a voltage source, in a second mode of operation. A second portion of the VGA provides a current path between a negative input and the negative output, and a current path either between the negative input and the positive output, in the first mode of operation, or between the negative input and the voltage source, in the second mode of operation. Control voltages selectively enable the paths in the first or second mode of operation. The control voltages further control amount of current flow in the enabled paths.