Filtering architectures and methods for wireless applications. In some embodiments, a wireless architecture can include a pre-amplifier filter configured to filter a signal, and an amplifier assembly configured to amplify the filtered signal. The wireless architecture can further include a filter circuit configured to provide selective filtering of the amplified signal based at least in part on a rejection level of the pre-amplifier filter and a gain of the amplifier assembly. In some embodiments, such a wireless architecture can be implemented in a packaged module or a wireless device.

A signal booster is disclosed. The signal booster can include a first gain unit with a first adjustable gain configured to be applied to a first-direction signal. The signal booster can include a second gain unit with a second adjustable gain configured to be applied to a second-direction signal. The signal booster can include a signal splitter communicatively coupled to the first gain unit and the second gain unit. The signal booster can include a control unit communicatively coupled to first gain unit and the second gain unit. The control unit can be configured to control the first adjustable gain and the second adjustable gain to compensate for a signal loss of the signal splitter.

The invention relates to an amplification circuit (100), comprising: a VGA (2), an AGC loop (10) for automatically controlling the gain of the VGA (2), a switching circuit (14) for switching between an AGC mode, in which the gain of the VGA (2) is automatically controlled by an output signal of the AGC loop (10) and a manual gain control, MGC, mode, in which the gain of the VGA (2) can be manually controlled by an input signal, and a read/write circuit (30) with a contact (31) for connection to a peripheral system, wherein the read/write circuit (30) is configured, in the MGC mode, to provide the input signal from the contact (31) via a write-mode path (32) to the VGA (2), and, in the AGC mode, to provide the output signal of the AGC loop (10) via a read-mode path (33) on the contact (31).

Systems and methods for dynamically adjusting the gain in a receiver front end to have a desired amount of headroom, based upon a measurement of the signal to noise ratio (SNR) of the output of a digital to analog converter and the amount of degradation to the SNR due to previous adjustments to the gain.

A system may comprise a high-pass filter having an input for receiving an input signal, an output for generating an output signal, a capacitor coupled between the input and the output, a switched-capacitor resistor coupled between the output and a reference voltage, and control circuitry configured to control the reference voltage to cancel current leakage into a circuit coupled to the output. The input, the output, the capacitor, and the switched-capacitor resistor may be arranged to generate the output signal as a high-pass filtered version of the input signal and the high-pass filter may be configured to operate in a plurality of modes comprising at least a high-impedance mode and a low-impedance mode in which the resistance of the switched-capacitor resistor is significantly smaller than the resistance when in the high-impedance mode.

A system may include a plurality of processing paths having a first path configured to generate a first digital signal based on an analog input signal and a second path configured to generate a second digital signal based on the analog input signal, the second path having a high-pass filter for filtering the analog input signal prior to the analog input signal being processed by the remainder of the second path, and the high-pass filter having a corner frequency. Control circuitry may be configured to determine frequency-dependent weighted proportions of the first and second digital signals to be combined into an output digital signal based on a characteristic of the analog input signal. Frequency-dependent weighted proportions may be such that the digital output signal includes spectral content of the first digital signal below the corner frequency to account for spectral content of the second digital signal below the corner frequency being filtered.

A system may include an input for receiving an input signal, an output for generating an output signal, a capacitor coupled between the input and the output, a variable resistor coupled to the output and having a plurality of modes including a first mode in which the variable resistor has a first resistance and a second mode in which the variable resistor has a second resistance, and control circuitry configured to determine a difference between the input signal and the output signal and switch between modes of the plurality of modes when the difference is less than a predetermined threshold.

Anti-jamming techniques are provided for RF receivers, such as those that operate in hostile environments. In some embodiments, the techniques are embodied in an anti-jam communications system configured with automatic gain control (AGC) that is complementary. The system includes a first AGC circuit prior to an interference suppression circuit and a second AGC circuit after the interference suppression circuit. The first AGC circuit operates to adjust the power level presented to the interference suppression circuit to facilitate interference cancellation. The second AGC circuit operates to maintain the original power level of the desired communications signal and prevent amplitude errors as the first AGC circuit responds to fluctuations in jammer signal power. The second AGC can be slaved to the first AGC circuit such that the sum of two gain values is held constant, according to some embodiments. In this manner, the first and second AGC circuits provide a complementary-AGC system.

The disclosure relates to technology for a fully differential adjustable gain device that includes differential input terminals, differential output terminals, fully differential signal processing circuitry, and first and second cross-coupled segments. The first cross-coupled segment is coupled between differential input terminals of the fully differential adjustable gain device and a negative input of the fully differential signal processing circuitry. The second cross-coupled segment is coupled between differential input terminals of the fully differential adjustable gain device and a positive input of the fully differential signal processing circuitry. The fully differential adjustable gain device has a gain that is adjustable by adjusting values of the first and second cross-coupled segments, while maintaining a substantially consistent frequency response and a substantially consistent input impedance of the fully differential adjustable gain device, so long as a specified relationship between values of the first and second cross-coupled segments is kept substantially constant.

Anti-jamming techniques are provided for RF receivers, such as those that operate in hostile environments. In some embodiments, the techniques are embodied in an anti-jam communications system configured with automatic gain control (AGC) that is complementary. The system includes a first AGC circuit prior to an interference suppression circuit and a second AGC circuit after the interference suppression circuit. The first AGC circuit operates to adjust the power level presented to the interference suppression circuit to facilitate interference cancellation. The second AGC circuit operates to maintain the original power level of the desired communications signal and prevent amplitude errors as the first AGC circuit responds to fluctuations in jammer signal power. The second AGC can be slaved to the first AGC circuit such that the sum of two gain values is held constant, according to some embodiments. In this manner, the first and second AGC circuits provide a complementary-AGC system.

A circuit arrangement for compensating for signal attenuation during the transmission of transmission signals of a mobile communications device includes at least one amplifier is switched out of the signal transmission path or is deenergized, or does not amplify, attenuate or forward the detected input signal, unless an input signal level is detected which is greater than or equal to the input signal detection level (S.sub.EP) or a trigger level (S.sub.AP) which is at most 10 dB higher than the same. Alternatively or in combination, the amplifier is operated at a variable amplification factor in an adjustment range (X1) which begins at an input signal detection level (S.sub.EP) or a trigger level (S.sub.AP) which is at most 10 dB higher than the same, and extends to cover higher signal levels than these, wherein, if the input signal detection level (S.sub.EP) or the trigger level (S.sub.AP) is reached or exceeded, the input signal is either non-amplified or is attenuated at an amplification factor?1.

An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.