A distributed antenna system interface tray (DIT) includes a plurality of per-carrier points of interface (POIs), a combiner, and a DIT management system (DMS). Each of the plurality of POIs may be configured to couple with a corresponding per-carrier base transceiver station (BTS), receive a per-carrier downlink (DL) signal from the corresponding BTS, filter the DL signal through a duplexer, adjust the filtered DL signal based on a designated level, output the filtered DL signal to a combiner, receive an uplink (UL) signal from the combiner, adjust the UL signal based on a designated gain, and transmit the UL signal to the corresponding BTS. The combiner may be configured to combine a plurality of DL signals received from the plurality of POIs into a combined DL signal, transmit the combined DL signal to a distributed antenna system, receive a UL signal from the distributed antenna system, and distribute the UL signal to the plurality of POIs.

A receiver front-end capable of receiving RF inputs having a broad range of levels. The receiver comprises a low-noise amplifier (LNA) operating in a variety of bias modes that cover a large gain range. Branches of the amplifier can be turned on in various combinations to allow selection of different bias modes. A degeneration inductor coupled to the source of the common source FET of each branch has a plurality of taps that are coupled to degeneration switches that can ground the tap to effectively shorten the degeneration inductor and reduce the amount of degeneration inductance. The degeneration inductor and associated switches can be fabricated using one of several physical layouts. Operating the degeneration switches to select the length of the degeneration inductor to match the bias mode reduces changes in the input impedance as different bias modes are selected.

A wireless device, method, and signal for use in communication of a wireless packet between transmitting device and a wireless receiving device via a plurality of antennas, wherein a signal generator generates wireless packet including a short-preamble sequence used for a first automatic gain control (AGC), a first long-preamble sequence, a signal field used for conveying a length of the wireless packet, an AGC preamble sequence used for a second AGC to be performed after the first AGC, a second long-preamble sequence, and a data field conveying data. The AGC preamble sequence is transmitted in parallel by the plurality of antennas.

A circuit may include at least one amplifier circuit configured to amplify a received signal having a first signal received in a first time interval and a second signal received in a second time interval. The first signal and the second signal are signals sent by a different number of coherent wireless signal sources. The circuit arrangement may further include at least one gain control circuit connected to the at least one amplifier circuit and configured to determine a first expected received signal strength of the first signal, to determine a second expected received signal strength of the second signal, and to determine a gain level based on the first and second expected received signal strengths. The at least one amplifier circuit may be configured to amplify the first signal using the determined gain level and to amplify the second signal using the determined gain level.

An AGC circuit for a radio receiver includes a detector converting a high frequency signal into a baseband signal. To reduce generation of a DC offset, the AGC circuit includes: a variable gain amplifier having an amplifier circuit and a high-pass filter, the amplifier circuit amplifying the baseband signal with a variable gain and the high-pass filter coupled to the amplifier circuit and having a cut-off frequency which is variable; a controller supplying a gain control signal; and a blocker temporarily blocking the high frequency signal. Using the block control signal, the controller causes the blocker to start blocking the high frequency signal, before the cut-off frequency of the high-pass filter is switched from high to low.

A gain controller sets a gain code indicating an optimum gain, a cutoff frequency code indicating a cutoff frequency, and a number of bits code indicating a number of bits. An AEQ/VGA gain controller sets a frequency characteristic code indicating a frequency characteristic, a gain code indicating a gain after correction, and a number of bits code indicating a number of bits. An AEQ/VGA amplifies a baseband received signal on the basis of a gain code and corrects a frequency characteristic of the baseband received signal on the basis of a frequency characteristic code. An HPF cuts off a band below a cutoff frequency of an output signal from the AEQ/VGA on the basis of a cutoff frequency code. An ADC quantizes an output signal from the HPF using a number of bits based on a number of bits code and generates a digital received signal.

There is a low-power multifrequency impedance analyzer based on a monolithic mixed-signal (analog/digital) microchip that performs all the tasks necessary to perform impedance measurements in the frequency range from 10 kHz to 10 MHz. In contrast to a full analog lock-in approach, this mixed-signal solution combines the lock-in approach with the dual step super-heterodyne demodulation scheme. The circuit ensures a CMRR of 81 dB@10 kHz, which increases to 84 dB@10 MHz. The measured equivalent input noise power spectral density is en=2.57 nV/Hz at 10 kHz in the worst case, close to the 1/f corner frequency. It decreases to en=1.8 nV/Hz at 1 MHz and en=1.9 nV/Hz at 10 MHz. Measurements of a reference RC network performed with the proposed low-cost low-power multifrequency impedance analyzer are compared with a Keysight E4980A Precision LCR Meter showing a maximal relative error of 0.8% over the whole operating frequency range.

A signal receiving apparatus includes a signal processing circuit, an adjacent-channel interference (ACI) filter and an ACI detecting circuit. The signal processing circuit performs a signal processing process on an input signal to generate a processed signal. The ACI filter filters out ACI from the processed signal to generate a filtered signal. The ACI detecting circuit detects an energy difference between the processed signal and the filtered signal, and provides the energy difference to the signal processing circuit as a reference for adjusting the signal processing process.

The wireless RF semiconductor system is described for use in wireless communication devices that operate in frequency range from 6 GHz to 100 GHz. The system comprises of at least one RF antenna and at least one active RF component fabricated (or built) on the same semiconductor substrate inside a one single packaged module. The wireless RF semiconductor system is described in a variety of different configurations with its functionality divided up over several single chip circuits. The system simplifies assembly, reduces size and cost, and allows for a quick time to market, while maximizing the RF performance demanded by fixed and mobile 4G, 5G and other wireless standards. The system uses a novel idea of design and packaging of active and passive RF components into a single package. This in turn allows RF designers to unlock the potential of very high frequencies operation that were previously thought too expensive and/or unattainable to average user. The wireless RF semiconductor system can be implemented in both mobile solutions (such as phones, tablets, and the like) and fixed applications (such as repeaters, base-stations, and distributed antenna system).

Embodiments of the present disclosure provide a method, a device, and a storage medium for hybrid automatic gain control in a communication system. The method includes amplifying an input signal to generate an amplified signal which is converted into a plurality of output signals; obtaining a moving average amplitude of a plurality of output signals of a current input signal; and calculating a signal amplitude difference according to the moving average amplitude and a desired output signal amplitude level; calculating a signal amplitude ratio according to a plurality of output signals of two previous output signal blocks and AGC gains corresponding to the plurality of output signals of the two previous output signal blocks; obtaining a step size according to the signal amplitude difference and the signal amplitude ratio; and calculating an AGC gain of the current input signal according to the step size and a corresponding previous AGC gain.