A fast switching time is highly desired in the design of mobile handsets. The limiting factor in the switching time is the resistor through which bias is applied to amplifiers used within such handsets. Bypassing the bias resistor when amplifiers are transitioning is a way to improve switching time without compromising the RF performance. Methods and devices to generate short pulses without relying on a continuously running clock and used to bypass bias resistors are described.

A local oscillator device includes an oscillator module including a first inductive element and a capacitive element coupled in parallel with the inductive element. A frequency divider is coupled to the oscillator module for delivering a local oscillator signal. The local oscillator device includes an autotransformer including the first inductive element and two second inductive elements respectively coupled to the terminals of the first inductive element and to two output terminals of the autotransformer, the output terminals being further coupled to input terminals of the frequency divider.

A receiver includes a low noise amplifier (LNA) configured to amplify an input RF signal using a first current supplied by a first current source, and a voltage controlled oscillator (VCO) for applying an oscillation frequency to the amplified signal by generating an oscillation signal using the first current.

A wireless receiver includes an analog-to-digital converter that converts a signal corresponding to a received signal into a digital signal on the basis of multiple reference voltages and outputs the digital signal. The wireless receiver also includes a control circuit that controls at least one of the multiple reference voltages on the basis of the digital signal that is output from the analog-to-digital converter.

A receiver has a differential transimpedance amplifier (4) with two inputs and two outputs. The differential transimpedance amplifier (4) provides a differential output and this is peak-detected (15, 16) to provide amplitude reference signals. The differential transimpedance amplifier output and the amplitude reference signals are fed to a differential summing amplifier (10), which provides a fully differential signal to a comparator, or to an automatic gain control circuit (5) to regulate the differential transimpedance amplifier gain. The differential summing amplifier (10) output is a fully differential signal, thereby having lower distortion for DC and burst mode receiver applications.

Systems and methods for dynamically adjusting the gain in a receiver front end to have a desired amount of headroom, based upon a measurement of the signal to noise ratio (SNR) of the output of a digital to analog converter and the amount of degradation to the SNR due to previous adjustments to the gain.

A circuit is formed on an SOI. The bias generator is connected to the gates of first and second transistors. In the bias generator, a first variable current source is connected to the power supply circuit via a power supply node. A third transistor is connected between the first variable current source and a ground-voltage source. A gate thereof is connected to the gate of the first transistor. A first operational amplifier controls a gate voltage of the third transistor so that a voltage at a second node between the first variable current source and the third transistor becomes almost equal to a reference-voltage. A first characteristics changer is connected to the gate of the third transistor or a second node, to change at least one loop gain characteristics and phase characteristics of a loop from the first operational amplifier, through the third transistor, to the first variable current source.

Embodiments of power detector circuits and related methods to compensate for undesired DC offsets generated within power detector circuits are disclosed. Input signals having input frequencies are received and converted to a magnitude signal, and reference signals are also generated. The magnitude signal may include a DC component proportional to a power of the input signal along with undesired DC offsets. The reference signal may include a DC component proportional to a power of at least one input reference signal along with undesired DC offsets. To compensate for errors introduced by the DC offsets, a DC offset calibration signal or a gain are determined in a calibration mode and then applied in a normal mode to compensate for the DC offsets. For the calibration mode, a difference between the magnitude signal and the reference signal is compared to a threshold value to generate a power detection output signal.

The present invention describes an amplifier adjusting device for an amplifier element which is adjustable as a function of amplification factor and is coupled to a frequency domain selecting element for adjusting at least to frequency domains. The amplifier adjusting device includes a memory in which at least two amplification factors may be stored, the at least two amplification factors being assigned to the two at least two frequency domains, an amplification factor adjusting element configured to select, depending on a current frequency domain, a corresponding amplification factor from the memory in order to adjust the adjustable amplifier element, and an amplification factor estimator configured to correct, based on an analysis of a signal amplified by means of the adjustable amplifier element in accordance with the selected amplification factor, the selected amplification factor and store the corrected amplification factor in the memory.

An automatic gain control circuit includes a reference level calculator that calculates a reference level on the basis of the amplitude of a reception signal; a resistor that stores an adjustment value for the reference level; a reference level adjuster that adjusts the reference level on the basis of the adjustment value stored in the resistor, and generates an adjusted reference level; and a bit width conversion circuit that performs a bit width conversion to reduce the bit width of the reception signal, on the basis of the adjusted reference level.