The disclosed technology is related to a radio-frequency (RF) amplifier having a bypass circuit and a resonant structure to improve performance in a bypass mode (e.g., a low gain mode). The disclosed amplifiers have a resonant structure that effectively isolates an amplifier core from a bypass circuit. For example, in a bypass mode, the resonant structure is configured to create an open impedance looking into the amplifier core input. This effectively removes any loading from the amplifier core to the bypass circuit. The disclosed amplifiers with resonant structures improve linearity performance in bypass modes due at least in part to the open impedance to the amplifier core provided by the resonant structure.

The disclosed technology is related to a radio-frequency (RF) amplifier having a bypass circuit and a resonant structure to improve performance in a bypass mode (e.g., a low gain mode). The disclosed amplifiers have a resonant structure that effectively isolates an amplifier core from a bypass circuit. For example, in a bypass mode, the resonant structure is configured to create an open impedance looking into the amplifier core input. This effectively removes any loading from the amplifier core to the bypass circuit. The disclosed amplifiers with resonant structures improve linearity performance in bypass modes due at least in part to the open impedance to the amplifier core provided by the resonant structure.

An amplification device includes an amplification circuit, an inductor, a regulator, and a impedance circuit. The amplification circuit has an input terminal for receiving a radio frequency signal, and an output terminal for outputting an amplified radio frequency signal. The inductor has a first terminal, and a second terminal coupled to the output terminal of the amplification circuit. The regulator is coupled to the first terminal of the inductor and generates a steady voltage and/or a steady current. The impedance circuit has a first terminal coupled to the output terminal of the amplification circuit, and a second terminal coupled to a first system voltage terminal. The impedance circuit provides a low frequency impedance path to suppress a beat frequency signal in the amplified radio frequency signal.

The detection matrix for an Orthogonal Differential Vector Signaling code is typically embodied as a transistor circuit with multiple active signal inputs. An alternative detection matrix approach uses passive resistor networks to sum at least some of the input terms before active detection.

Embodiments provide an audio amplifier circuit with integrated (built-in) filter (e.g., a digital-to-analog converter (DAC) filter). The audio amplifier circuit may have a non-flat (e.g., low-pass) closed loop frequency response. The audio amplifier circuit may include a low pass filter coupled between an input terminal that receives the input analog audio signal and the input of the gain stage of the amplifier. In some embodiments, additional impedance networks may be included to produce a desired low-pass filter response, such as a second order filter, a third order filter, and/or another suitable filter response. Other embodiments may be described and/or claimed.

Provided is an amplification circuit for amplifying an input signal. The amplification circuit includes an input stage including an input matching circuit that receives the input signal and an input attenuation circuit that attenuates a gain for the input signal outside an operating frequency band of the amplification circuit, a transistor that amplifies the input signal provided from the input stage, and an output stage including an output matching circuit that receives a signal amplified by the transistor and an output attenuation circuit that attenuates the gain for the input signal outside the operating frequency band of the amplification circuit, and the input attenuation circuit includes a first resistor and a second resistor that are connected to a ground voltage, a first passive element connected between the input matching circuit and the second resistor, and a second passive element connected between the first passive element and the first resistor.

Equalizer circuitry includes a differential target voltage input, an equalizer output, a first operational amplifier, and a second operational amplifier. The differential target voltage input includes a target voltage input node and an inverted target voltage input node. The first operational amplifier and the second operational amplifier are coupled in series between the differential target voltage input and the equalizer output. The first operational amplifier is configured to receive a target voltage signal and provide an intermediate signal based on the target voltage input signal. The second operational amplifier is configured to receive the intermediate signal and an inverted target voltage signal and provide an output signal to the equalizer output. The first operational amplifier and the second operational amplifier are interconnected with one or more passive components such that a transfer function between the differential target voltage input and the equalizer output is a second-order complex-zero function.

A method of controlling bandwidth and peaking over gain in a variable gain amplifier (VGA) device and structure therefor. The device includes at least three differential transistor pairs configured as a cross-coupled differential amplifier with differential input nodes, differential bias nodes, differential output nodes, a current source node, and two cross-coupling nodes. The cross-coupled differential amplifier includes a load resistor coupled to each of the differential output nodes and one of the cross-coupling nodes, and a load inductor coupled to the each of the cross-coupling nodes and a power supply rail. A current source is electrically coupled to the current source node. The cross-coupling configuration with the load resistance and inductance results in a lower bandwidth and lowered peaking at low gain compared to high gain. Further, the tap point into the inductor can be chosen as another variable to tune the bandwidth and peaking in a communication system.

A low-voltage high-speed programmable equalization circuit includes a gain boosting amplifier stage, a CML differential amplifier stage, and an emitter follower. An input terminal of the gain boosting amplifier stage serves as an input terminal of the equalization circuit. An output terminal of the gain boosting amplifier stage is connected to an input terminal of the CML differential amplifier stage. An output terminal of the CIVIL differential amplifier stage is connected to an input terminal of the emitter follower. An output terminal of the emitter follower serves as an output terminal of the equalization circuit.

A receiver front-end includes a first variable-gain amplifier that performs attenuation; a continuous time linear equalizer coupled to the input or output of the first variable-gain amplifier, wherein a combination of the first variable-gain amplifier and the continuous time linear equalizer produces a processed signal; a plurality of track-and-hold circuits that sample the processed signal in an interleaved manner; and a plurality of second variable-gain amplifiers receiving input signals from the plurality of track-and-hold circuits respectively.