A filter device includes: a common terminal; a first input/output terminal; a second input/output terminal; a first filter connected to a first path that connects the common terminal and the first input/output terminal, and having a passband that is a first band; a second filter connected to a second path that connects the common terminal and the second input/output terminal, and having a passband that is a second band having a frequency range that is different from and does not overlap a frequency range of the first band; a first switch element connected between a first node on the first path between the first filter and the first input/output terminal and a second node on the second path between the second filter and the second input/output terminal; and a second switch element on the second path, which is connected between the second node and the second input/output terminal.

Fabrication of superconducting devices that combine or separate direct currents and microwave signals is provided. A method can comprise forming a direct current circuit that supports a direct current, a microwave circuit that supports a microwave signal, and a common circuit that supports the direct current and the microwave signal. The method can also comprise operatively coupling a first end of the direct current circuit and a first end of the microwave circuit to a first end of the common circuit. The direct current circuit can comprise a bandstop circuit and the microwave circuit can comprise a capacitor. Alternatively, the direct current circuit can comprise a bandstop circuit and the microwave circuit can comprise a bandpass circuit. Alternatively, the microwave circuit can comprise a capacitor and the direct current circuit can comprise one or more quarter-wavelength transmission lines.

A band-pass filter (BPF) includes a pair of coupled transformers including first through fourth conductive structures. The first conductive structure includes a first terminal and two first extending portions extending from the first terminal and configured as primary windings. The second conductive structure includes a second terminal and two second extending portions extending from the second terminal. A first via connects the third conductive structure to a first one of the two second extending portions, the third conductive structure and the first one of the two second extending portions thereby being configured as a first secondary winding. A second via connects the fourth conductive structure to a second one of the two second extending portions, the fourth conductive structure and the second one of the two second extending portions thereby being configured as a second secondary winding.

An interdigitated RF filter. The interdigitated RF filter includes input fingers connected to an input node and output fingers connected to an output node where at least one input finger is connected the output node or at least one output finger is connected to the input node. The described interdigitated RF filter can be implemented in various configurations such as series, shunt, ladder or a combination thereof.

An RF power detector adapted to detect an RF power of an RF signal, includes, in part, an antenna adapted to receive the RF signal, a narrow-band RF power converter adapted to convert the RF signal to a DC signal, an accelerometer, and a magnetometer. The accelerometer and magnetometer are adapted to determine the orientation and location of the power detector. The power detector optionally includes a gyroscope. The narrow-band RF power converter may be a rectifier tuned to the frequency of the RF signal. The power detector optionally includes an indicator adapted to provide information representative of the amount of the DC power of the DC signal, as well as position and orientation of the power detector. The power detector may be adapted to be inserted into a mobile device so as to provide the information about the amount of DC power, orientation and position to the mobile device.

A filter circuit includes a pair of balanced input ports, a pair of balanced output ports, and first and second resonators provided in parallel between the pair of balanced input ports and the pair of balanced output ports in a circuit configuration, the first and second resonators being magnetically coupled to each other. Between the first resonator and the second resonator, a capacitor is present but no inductor is present in the circuit configuration.

A digital decimation filtering circuit of an analog to digital conversion circuit includes an n-tap anti-aliasing filter operable to receive a 1-bit analog to digital converter (ADC) output signal at an oversampling rate and filter the 1-bit ADC output signal to remove frequencies higher than a selected cut-off frequency to produce an n-bit filtered signal at a first data output rate. The digital decimation filtering circuit further includes a decimator operable to receive the n-bit filtered signal at the first data output rate, decimate the n-bit filtered signal by a decimation factor to produce a set of output signals, and sum the set of outputs to produce a decimated signal at a second data output rate. The first data output rate is greater than the second data output rate.

An electronic circuit includes a first filter and a second filter. The first filter passes a first frequency component of a first harmonic frequency generated by a first voltage source to form a potential difference in a chamber and a second frequency component of a second harmonic frequency higher than the first harmonic frequency. The second filter removes the first frequency component and the second frequency component received from the first filter. The second harmonic frequency is included in a first frequency band determined based on a capacitance of the second filter.

A ladder filter includes series-arm resonators each including an IDT electrode and a reflector, and a parallel-arm resonator. In at least one of the series-arm resonators, where a wavelength that is determined by an electrode finger pitch of the IDT electrode is λ, an electrode finger center-to-center distance between an electrode finger located closest to the reflector among electrode fingers of the IDT electrode and an electrode finger located closest to the IDT electrode among electrode fingers of the reflector is less than about 0.5λ, and an anti-resonant frequency of the at least one of the series-arm resonators is higher than an anti-resonant frequency of at least another one of the series-arm resonators.

Systems, devices, and methods for adjusting tuning settings of tunable components, such as tunable capacitors, can be configured for calibrating a tunable component. Specifically, the systems, devices and methods can measure a device response for one or more inputs to a tunable component, store a calibration code in a non-volatile memory that characterizes the device response of the tunable component, and adjust a tuning setting of the tunable component based on the calibration code to achieve a desired response of the tunable component.