The present invention discloses a common mode noise restrainer applicable to Ethernet, comprising: a circuit side configured to connect with an integrated circuit; a cable side configured to connect with a cable; a plurality of transformers set between the circuit side and the cable side; and a plurality of common mode chokes composed of a first part of the common mode chokes and a second part of the common mode chokes in which the first part of the common mode chokes is set between the circuit side and the plurality of transformers and the second part of the common mode chokes is set between the cable side and the plurality of transformers while the one or more transformer(s) connected with the first part of the common mode chokes are not identical to the one or more transformer(s) connected with the second part of the common mode chokes.

An electronic component having a multilayer body that includes a plurality of insulating layers that are stacked on top of one another; a primary coil and a secondary coil that are arranged inside the multilayer body in a stacking direction of the multilayer body; a first ground electrode and a second ground electrode that are provided in the multilayer body and between which the primary coil and the secondary coil are interposed in the stacking direction; and a ground terminal that is connected to the first ground electrode and the second ground electrode. A capacitance is generated between the first ground electrode and the primary coil or the secondary coil and a capacitance is generated between the second ground electrode and the primary coil or the secondary coil.

A circuit is provided, including first and second input terminals (110, 112) an output terminal (114), a DC-to-DC converter (120), and a trifilar choke (130) including a first inductor (140) connected between the first input terminal (110) and a first input terminal (150) of the converter (120), a second inductor (142) connected between the second input terminal (112) and a second input terminal (152) of the converter (120), and a third inductor (144) connected between the output terminal (114) and an output terminal (154) of the converter (120). The converter (120) is configured to convert a first voltage (V.sub.1) received at its first and second input terminals (150, 152) to a second voltage (V.sub.2) at its output terminal (154) higher than the first voltage (V.sub.1). The first, second and third inductors (140, 142, 144) are wound on a same core, mutually coupled and arranged such that currents common to the first and second inductors (140, 142) and currents common to the second and third inductors (142, 144) are blocked or attenuated. A current-limiting device, battery modules and a method of noise filtering are also provided.

An input buffer includes a pair of input transistors and associated injection circuits. A first input transistor has a source coupled to a first voltage rail through a first current source and a gate coupled to a first wire of a multi-wire serial bus. Three or more resistors in a first injection circuit couple the wires of the serial bus to a first common node, which is coupled to the source of the first input transistor by a first capacitor. A second input transistor has a source coupled to the first voltage rail through a second current source and a gate coupled to a second wire of the serial bus. Three or more resistors in a second injection circuit couple the wires of the multi-wire serial bus to a second common node, which is coupled to the source of the second input transistor by a second capacitor.

Disclosed herein is a thin film type common mode filter including: a base substrate made of an insulating material; a first insulating layer formed on the base substrate; a coil-shaped internal electrode formed on the first insulating layer; a second insulating layer formed on the internal electrode; an external electrode terminal having a vertical section connected to a side surface of the internal electrode and a horizontal section extended from an upper end of the vertical section toward a horizontal direction to thereby form a parallel surface spaced apart from the internal electrode by a predetermined distance; and a ferrite resin layer formed between the horizontal section of the external electrode terminal and the internal electrode.

A parallel via design is disclosed to improve the impedance match for embedded common mode choke filter designs. Particularly suited to such designs on four-layer printed circuit boards, the parallel via design effectively suppresses the reflection of the differential pair. By connecting the vias in parallel, the inductance of the entire via structure is reduced while its capacitance is simultaneously increased. By properly choosing the number of parallel vias and the spacing between them, the impedance of the parallel vias can be well controlled within the frequency range of interest. Consequently, the impedance match can be improved and the return loss of a four-layer printed circuit board common mode choke filter design is reduced.

Provided is a communication apparatus according to which the degree of balance between two electric wires on which a signal is sent can be increased. A communication apparatus transmits and receives a superposed signal via a control line and a ground line. In the communication apparatus, a common-mode noise filter removes common-mode noise from the superposed signal. A LPF extracts the charge control signal from the superposed signal from which the common-mode noise is removed, and outputs the extracted charge control signal to a charge control apparatus. The BPF extracts a communication signal from the superposed signal from which the common-mode noise is removed, and outputs the extracted communication signal to a communication unit via a protective circuit and a conversion circuit.

A transmission line includes three wires formed on a substrate. Each of the transmission lines transmits a three-level signal. A common-mode choke coil is inserted into the transmission line. The common-mode choke coil includes three coils coupled to one another and three pairs of outer electrodes, each of the three pairs being connected to the corresponding two ends of the coils. The outer electrodes of the common-mode choke coil are connected to the transmission line such that the three coils are serially inserted into the respective three wires.

A coil component includes a magnetic body having a plurality of filter parts disposed on a substrate and spaced apart from each other in a thickness direction. A plurality of input terminals and output terminals are disposed on outer surfaces of the magnetic body. Each of the filter parts includes upper and lower coils disposed in the magnetic body and spaced apart from each other in the thickness direction. In one example, a number of turns of the upper and lower coils of one filter part is different from a number of turns of the upper and lower coils of another filter part adjacent thereto. In another example, the number of turns of the upper and lower coils of the one and the other filter parts are the same, but capacitances of the one and the other filter parts are different.

A transformer filter arrangement (30) for passing signals at a fundamental frequency and suppressing signals at one or more interfering frequencies is disclosed. It comprises a transformer (100) having a first winding (110) and a second winding (120), wherein the first winding (110) has a first end (112a) and a second end (122b) and the second winding (120) has a first end (122a) and a second end (122b). It further comprises one or more capacitors (130a-e). For each capacitor (130a-c) of a first set of at least one capacitor of the one or more capacitors (130a-e), the capacitor (130a-c) is connected between a pair of taps (a1, a2; b1, b2; c1, c2) of the first winding (110), wherein each tap (a1, a2, b1, b2, c1, c2) of the pair of taps (a1, a2; b1, b2; c1, c2) is located between the first end (112a) and the second end (112b) of the first winding (110), and the capacitor (130a-c), together with an inductive sub segment (140a-c) of the first winding (110), which is connected in parallel with the capacitor (130a-c) between the pair of taps (a1, a2; b1, b2; c1, c2), forms a parallel LC circuit which is tuned to resonate at one of said interfering frequencies for suppressing signals at said one of the interfering frequencies. A corresponding integrated circuit, a corresponding radio receiver circuit, a corresponding radio transmitter circuit, and a corresponding radio communication apparatus are also disclosed.