Systems, devices, and methods including a first band-pass filter configured to receive and filter a detector signal, where the first band-pass filter has a central frequency of 2f; a second band-pass filter configured to receive and filter the detector signal where the second band-pass filter has a central frequency of 1f; a first logarithmic amplifier (Log Amp) configured to apply the filtered detector signal from the first band-pass filter; a second Log Amp configured to apply the filtered detector signal from the second band-pass filter; a differential amplifier configured to subtract the applied signal from the first Log Amp from the applied signal from the second Log Amp; and an Anti-Log Amplifier configured to determine an inverse logarithm of the subtracted signal from the differential amplifier.

A first and second input tone are applied to a continuous-time complex filter within an integrated circuit. The magnitude of the output of the filter at the frequency of each of the first and second input tones are measured and compared to determine the value of a filter tuning control signal. A tuning control signal is applied to the filter with the determined value to tune the filter.

The present disclosure relates to a concept of nonlinear signal processing which may be used for predistortion for RF power amplifiers. The concept includes generating time variant filter coefficients for a linear filter circuit based on a nonlinear mapping of an input signal, and filtering the input signal with the linear filter circuit using the time variant filter coefficients in order to generate a filtered output signal. Thus, it is proposed to implement a non-linear filter by a time-varying linear filter where the time-varying coefficients are derived from the input signal.

Certain aspects of the present disclosure relate to multi-band filter architectures and methods for filtering signals using the multi-band filter architectures. One example multi-band filter generally includes a transconductance-capacitance (gm-C) filter and a reconfigurable load impedance coupled to an output of the gm-C filter, the reconfigurable load impedance comprising a first gyrator circuit coupled to a second gyrator circuit.

A filter circuit may include a first path having a first complex baseband filter. The circuit may further include a second path having a second complex baseband filter. The circuit may further include a combiner coupled to an output of the first complex baseband filter and an output of the second complex baseband filter.

A circuit for digital filtering an analog signal converted to digital, including an analog circuit to generate an analog signal, the analog signal including phase and/or gain errors. An analog-to-digital converter (ADC) to convert the analog signal to a digital signal output to a digital signal path. A frequency-dependent corrector filter included in the digital signal path, and configured as a parameterized filter, the parameterized filter configurable based on the DSA control signal with at least one complex filter parameter for each DSA attenuation step, to correct frequency-dependent errors in phase and/or gain.

Systems, devices, and methods including a first band-pass filter configured to receive and filter a detector signal, where the first band-pass filter has a central frequency of 2f; a second band-pass filter configured to receive and filter the detector signal, where the second band-pass filter has a central frequency of 1f; a first logarithmic amplifier (Log Amp) configured to apply the filtered detector signal from the first band-pass filter; a second Log Amp configured to apply the filtered detector signal from the second band-pass filter; a differential amplifier configured to subtract the applied signal from the first Log Amp from the applied signal from the second Log Amp; and an Anti-Log Amplifier configured to determine an inverse logarithm of the subtracted signal from the differential amplifier.

The disclosure provides a switchable filtering circuit and the related operation method, in particular related to a filtering circuit which can be used for Bluetooth system and wireless local area network system. By using a first switch, a hybrid filtering circuit and a second switch, the received mode and transmitted mode between these two systems is realized. Moreover, the frequency responses and the bandwidth adjustments can be controlled according to the plurality of switchable resistors, the plurality of switchable capacitors and the shared and switchable resistors within the hybrid filter circuit. Moreover, the effects of high operated freedom of the circuit and the circuit size reduction can be achieved.

According to one embodiment, in a complex band pass filter, a second input signal to be supplied to a second active filter circuit has a substantially 90 degree phase difference from a first input signal to be supplied to a first active filter circuit. The first feedback circuit includes a first element having a first impedance and feeds back an output signal of the first active filter circuit to input side of the second active filter circuit. The second feedback circuit includes a second element having a second impedance different from the first impedance and feeds back an output signal of the second active filter circuit to input side of the first active filter circuit. The output circuit outputs an output signal according to a signal from the first active filter circuit and to a signal from the second active filter circuit.

The ABB blocks 332, 334, 336, and 318 are configured to process the I/Q signals corresponding to the first or the second HB independently or the I/Q signals corresponding to the LB in cooperation by two. In detail, the first ABB I block 332 and the first ABB Q block 334 operate independently in the 3G/4G mode but they are configured to process the I signal (or Q signal) of the LB in the 2G mode. Likewise, the second ABB Q block 336 and the second ABB I block 318 operate independently in the 3G/4G mode but they are configured to process the Q signal (or I signal) of the LB in the 2G mode. The first ABB I/Q blocks 332 and 334 and the second ABB I/Q blocks 336 and 318 are arranged symmetrically to processing the I/Q signals cooperatively in the 2G mode. In detail, the second ABB Q block 336 is arranged close to the first ABB Q block 334 such that the capacitor regions included in the first ABB I/Q blocks 332 and 334 are connected to each other and the capacitor regions included in the second ABB I/Q blocks 336 and 338 are connected to each other.