An apparatus comprises a first RF port, a second RF port, a first resonator circuit and at least one second resonator circuit. The first resonator circuit and the second resonator circuit may be connected between the first RF port and the second RF port. The first resonator circuit may comprise a first inductor, a first capacitor, and a first stacked switch device. The second resonator circuit may comprise a second inductor, a second capacitor, and a second stacked switch device. The first capacitor and the first stacked switch device may be coupled in series across the first inductor. The second capacitor, the second inductor, and the second stacked switch device may be connected in parallel.

An apparatus comprises a first RF port, a second RF port, a first resonator circuit and at least one second resonator circuit. The first resonator circuit and the second resonator circuit may be connected between the first RF port and the second RF port. The first resonator circuit may comprise a first inductor, a first capacitor, and a first stacked switch device. The second resonator circuit may comprise a second inductor, a second capacitor, and a second stacked switch device. The first capacitor and the first stacked switch device may be coupled in series across the first inductor. The second capacitor, the second inductor, and the second stacked switch device may be connected in parallel.

A driver circuit includes a first deglitcher circuit that delays a rising edge or a falling edge of an input signal according to a mode control signal and supplies a first output signal. A second deglitcher circuit receives the first output signal and delays either a rising edge or a falling edge of the first output signal by a second delay according to the mode control signal and supplies a second output signal. Logic gates combine the first and second output signals to supply gate control signals for output transistors to drive the driver circuit output. A sum of the first delay and the second delay determines the total deglitch time defining a pulse width of pulses that are suppressed by the driver circuit and the second delay determines a non-overlap time. The non-overlap time overlaps in time with the total deglitch time.

A circuit for digital filtering an analog signal converted to digital, including an analog circuit to generate an analog signal, the analog signal including phase and/or gain errors. An analog-to-digital converter (ADC) to convert the analog signal to a digital signal output to a digital signal path. A frequency-dependent corrector filter included in the digital signal path, and configured as a parameterized filter, the parameterized filter configurable based on the DSA control signal with at least one complex filter parameter for each DSA attenuation step, to correct frequency-dependent errors in phase and/or gain.

A circuit for digital filtering an analog signal converted to digital, including an analog circuit to generate an analog signal, the analog signal including phase and/or gain errors. An analog-to-digital converter (ADC) to convert the analog signal to a digital signal output to a digital signal path. A frequency-dependent corrector filter included in the digital signal path, and configured as a parameterized filter, the parameterized filter configurable based on the DSA control signal with at least one complex filter parameter for each DSA attenuation step, to correct frequency-dependent errors in phase and/or gain.

A tank circuit (200) includes a tunable resonator subcircuit (210) having a first control input and having an effective parallel resistance that varies with tuning of the tunable resonator subcircuit (210). The tank circuit (200) further comprises a variable negative-resistance subcircuit (250) having a second control input and coupled in parallel to the tunable resonator subcircuit (210), where the variable negative-resistance subcircuit (250) is configured to provide a variable negative resistance, responsive to the control input, so as to increase the effective parallel resistance of the tank circuit (200).

A tunable multi-path filter, a method for filtering a radio frequency signal with the tunable multi-path filter, and a communication device including the tunable multi-path filter. In one embodiment, the tunable multi-path filter includes a voltage controlled current source, an oscillator source, and at least two filter paths. The voltage controlled current source for receiving a radio frequency (RF) signal and generating a current signal. The oscillator source for generating a tunable clock signal. Each of the at least two filter paths are coupled to the voltage controlled current source and the oscillator source, and are configured to generate an output voltage signal based at least in part on the current signal and the tunable clock signal. In some embodiments, the tunable multi-path filter further includes a carrier signal rejection component that is configured to reduce the carrier feedthrough in the output voltage signals.

A tunable multi-path filter, a method for filtering a radio frequency signal with the tunable multi-path filter, and a communication device including the tunable multi-path filter. In one embodiment, the tunable multi-path filter includes a voltage controlled current source, an oscillator source, and at least two filter paths. The voltage controlled current source for receiving a radio frequency (RF) signal and generating a current signal. The oscillator source for generating a tunable clock signal. Each of the at least two filter paths are coupled to the voltage controlled current source and the oscillator source, and are configured to generate an output voltage signal based at least in part on the current signal and the tunable clock signal. In some embodiments, the tunable multi-path filter further includes a carrier signal rejection component that is configured to reduce the carrier feedthrough in the output voltage signals.

A tank circuit includes a tunable resonator subcircuit having an effective parallel resistance that varies with tuning of the tunable resonator subcircuit. The tank circuit further comprises a variable negative-resistance subcircuit coupled in parallel to the tunable resonator subcircuit, where the variable negative-resistance subcircuit is configured to provide a variable negative resistance, so as to increase the effective parallel resistance of the tank circuit. A control circuit is configured to increase the negative resistance presented by the variable negative-resistance subcircuit in response to a change in the tunable resonator subcircuit that lowers the resonant frequency of the tunable resonator subcircuit.

A hybrid filter circuit for reducing common-mode interference signals with frequencies of at least 150 kHz in a power line with at least one phase. The circuit has a passive filter stage and an active filter unit with an active filter stage. The circuit can be coupled to an electrical device on a load side and to a power supply system on a supply side via the power line. The first active filter stage includes a sensor for measuring a common mode noise signal in the power line and a feedback unit with an active amplifier unit for generating a compensation signal counteracting the common mode noise signal, which is coupled into the power line via an output of the first active filter stage. The passive filter stage and the active filter circuit are arranged in cascade between the load terminal and a supply terminal.