An error amplifier for a pulse width modulation circuit is described. The amplifier includes an operational amplifier configured as an integrator and a feedback loop coupled between a signal output of the operational amplifier and an inverting input of the operational amplifier. The feedback loop comprises a feedback capacitor coupled to the signal output, a feedback resistor coupled to the feedback capacitor, and an integrator resistor coupled to the feedback resistor and the inverting input of the operational amplifier. A junction between the feedback resistor and the integrator resistor is configured to receive an input signal and a junction between the feedback capacitor and the feedback resistor is configured to receive a feedback signal from the pulse width modulation circuit.

Systems and methods for converting a capacitance signal into a band-limited voltage signal for improved signal processing are disclosed herein. Such systems can include a capacitance-to-voltage converter configured to convert a capacitive signal from a capacitive device that operates at a mechanical frequency into a raw voltage signal, a clock generator configured to convert the mechanical frequency into one or more clock signals, and a filter component configured to apply a band-pass filter response to the raw voltage signal to convert the raw voltage signal into a band-limited voltage signal. The clock generator can be configured to apply the one or more clock signals to the filter component to drive a first pole and a second pole of the band-pass filter response to track the mechanical frequency of the capacitive device such that the geometric mean of the first pole and the second pole is substantially equal to the mechanical frequency.

A filter and an operating method thereof are provided. The filter includes a logic circuit, a power circuit and a filter circuit. The logic circuit provides a switching control signal. The power circuit is coupled to the logic circuit. The filter circuit is coupled to the power circuit and the logic circuit. The filter circuit includes an amplifier, a first capacitor and a first transistor. An output end of the amplifier is coupled to the logic circuit, and provides an output signal. The first capacitor is coupled between an input end and output end of the amplifier. The first transistor is connected in parallel with the first capacitor. A control end of the first transistor is coupled to the power circuit. The logic circuit provides a switching control signal to the power circuit according to the output signal. The power circuit supplies a control voltage to the first transistor according to the switching control signal. Therefore, the filter of the present invention and its method of operation can provide an accurate filtered signal output function.

A filter and an operating method thereof are provided. The filter includes a logic circuit, a power circuit and a filter circuit. The logic circuit provides a switching control signal. The power circuit is coupled to the logic circuit. The filter circuit is coupled to the power circuit and the logic circuit. The filter circuit includes an amplifier, a first capacitor and a first transistor. An output end of the amplifier is coupled to the logic circuit, and provides an output signal. The first capacitor is coupled between an input end and output end of the amplifier. The first transistor is connected in parallel with the first capacitor. A control end of the first transistor is coupled to the power circuit. The logic circuit provides a switching control signal to the power circuit according to the output signal. The power circuit supplies a control voltage to the first transistor according to the switching control signal. Therefore, the filter of the present invention and its method of operation can provide an accurate filtered signal output function.

A receiving device for receiving PLC signals, including a filtering stage linked to an input of the receiving device and configurable in at least two modes including a default mode, wherein the filtering stage passes at least first PLC signals included in a first frequency band and second PLC signals included in a second frequency band separate from the first frequency band, and a first selection mode, in which the filtering stage passes the first PLC signals and stops the second PLC signals; and a processing circuit linked to the filtering stage and arranged to receive frames of PLC signals, and, for each received frame, to analyse a preamble of the frame, and to dynamically configure the filtering stage in the first selection mode if the frame is a frame of first PLC signals.

A mixer module includes a mixer, at least one DC offset circuit, a filter and a controller. The mixer mixes an input signal to generate a first signal. The at least one DC offset circuit generates a second signal based on the first signal. The filter filters out an AC portion of the second signal and generates a third signal according to a DC portion of the second signal. The controller controls the at least one DC offset circuit based on the third signal to reduce a DC portion of the first signal.

Aspects of the disclosure are directed to auto-sweeping impedance-matching circuitry that matches an impedance of an RF antenna. As may be implemented in accordance with one or more embodiments, a transmitter that is configured and arranged to transmit signals to remote devices via the RF antenna, is used to communicate a plurality of test signals to the impedance-matching circuitry, with each test signal having a designated frequency and/or test signal pattern that is different than the designated frequency and/or test signal pattern of the other test signals. A characteristic of each of the test signals as passed through the impedance-matching circuitry is detected. For each of the test signals generated for the auto-sweep, the detected characteristic is compared to an expected characteristic for the test signal, and an output indicative of compliance of the impedance-matching circuitry with a design specification is generated and transmitted in response to the comparison.

A method of stabilizing a variable filter for an analog electromagnetic signal against circuit oscillation includes the steps of: providing a signal loop comprising a signal input, a signal output, and a plurality of variable circuit elements connected in the signal loop, the plurality of variable circuit elements comprising an adjustable resonator and an adjustable gain block, the signal loop having a variable frequency response that is characterized by a central frequency, a frequency passband, a response Q, and an operating point and a resonator response curve that are plottable in a Cartesian s-plane having an origin, a real axis, and an imaginary axis; and maintaining stability of the variable filter within an operating range by controlling the adjustable resonator and the adjustable gain block such that, in the Cartesian s-plane, the resonator response curve satisfies an orthogonality stability condition.

A method and apparatus for modifying or controlling a resonator connected to a signal loop having an input (18828), an output (18822), and a closed loop frequency response. The signal loop has a primary resonator (18810) having a primary frequency response. There is at least one adjustable resonator (18812) having an adjustable frequency (f) and a secondary Q-factor. An adjustable scaling block (18824) applies a gain factor (g). A controller is connected to the at least one adjustable resonator (18812) and the adjustable scaling block (18824). The controller has instructions to adjust the closed loop frequency response toward a desired closed loop frequency response by controlling the adjustable frequency (f) of the at least one adjustable resonator (18812) and the gain factor (g) of the adjustable scaling block (18824).

A method and apparatus for modifying or controlling a resonator connected to a signal loop having an input (18828), an output (18822), and a closed loop frequency response. The signal loop has a primary resonator (18810) having a primary frequency response. There is at least one adjustable resonator (18812) having an adjustable frequency (f) and a secondary Q-factor. An adjustable scaling block (18824) applies a gain factor (g). A controller is connected to the at least one adjustable resonator (18812) and the adjustable scaling block (18824). The controller has instructions to adjust the closed loop frequency response toward a desired closed loop frequency response by controlling the adjustable frequency (f) of the at least one adjustable resonator (18812) and the gain factor (g) of the adjustable scaling block (18824).