A phase shifter includes: a first transistor including a first source and a first drain; a second transistor including a second source and a second drain; a first inductor connected with the first source and the first drain, connected in parallel with the first transistor, and including a first body part having an interrupted part, and a first connection part formed at the interrupted part; a second inductor connected with the second source and the second drain, connected in parallel with the second transistor, and including a second body part having an interrupted part, and a second connection part formed at the interrupted part; an inspection drain terminal connected with the first drain and the second drain; and an inspection source terminal connected with the first source and the second source.

A variable gain phase shifter includes an I/Q generator and a vector summation circuit. The I/Q generator generates phase signals based on an input signal. The vector summation circuit adjusts magnitudes and directions of first, second, third and fourth in-phase vectors and first, second, third and fourth quadrature vectors, and generates an output signal by summing the in-phase vectors and the quadrature vectors, based on the phase signals, selection signals and current control signals. The vector summation circuit includes first, second, third and fourth vector summation cells and first, second, third and fourth current control circuits. The first and second vector summation cells adjust the directions of the first and second in-phase vectors and the first and second quadrature vectors. The third and fourth vector summation cells adjust the directions of the third and fourth in-phase vectors and the third and fourth quadrature vectors. The first and second current control circuits are connected to the first and second vector summation cells, and adjust an amount of a first current and an amount of a second current. The third and fourth current control circuits are connected to the third and fourth vector summation cells, and adjust an amount of a third current and an amount of a fourth current.

A variable gain phase shifter includes an I/Q generator and a vector summation circuit. The I/Q generator generates phase signals based on an input signal. The vector summation circuit adjusts magnitudes and directions of first, second, third and fourth in-phase vectors and first, second, third and fourth quadrature vectors, and generates an output signal by summing the in-phase vectors and the quadrature vectors, based on the phase signals, selection signals and current control signals. The vector summation circuit includes first, second, third and fourth vector summation cells and first, second, third and fourth current control circuits. The first and second vector summation cells adjust the directions of the first and second in-phase vectors and the first and second quadrature vectors. The third and fourth vector summation cells adjust the directions of the third and fourth in-phase vectors and the third and fourth quadrature vectors. The first and second current control circuits are connected to the first and second vector summation cells, and adjust an amount of a first current and an amount of a second current. The third and fourth current control circuits are connected to the third and fourth vector summation cells, and adjust an amount of a third current and an amount of a fourth current.

The present application relates to a method and apparatus for implementing a radar array including a gate bias source for providing a first variable voltage, a back gate well control for providing a second variable voltage, and a field effect transistor having a drain, a source, a gate and a back gate well control, the field effect transistor being further configured to couple an alternating current radar signal between the drain and the source and to adjust a phase of the alternating current radar in response to first variable voltage applied to the gate and the second variable voltage applied to the back gate well control.

The present application relates to a method and apparatus for implementing a radar array including a gate bias source for providing a first variable voltage, a back gate well control for providing a second variable voltage, and a field effect transistor having a drain, a source, a gate and a back gate well control, the field effect transistor being further configured to couple an alternating current radar signal between the drain and the source and to adjust a phase of the alternating current radar in response to first variable voltage applied to the gate and the second variable voltage applied to the back gate well control.

First and second paths (I,II) are connected in parallel between an input terminal (IN) and an output terminal (OUT). A high-pass filter (HPF) is provided in the first path (I). A low-pass filter (LPF) is provided in the second path (II). A switch (SW1-SW4) connects one of the high-pass filter (HPF) and the low-pass filter (LPF) to the input terminal (IN) and the output terminal (OUT) and disconnects the other. A transmission line (TL1,TL2) is provided on the first and second paths (I,II) respectively. A line length of the transmission line (TL1,TL2) is adjusted such that a resonance caused due to circuit constants of the high-pass filter (HPF) and the low-pass filter (LPF) and capacitance obtained when the switch (SW1-SW4) is OFF is shifted to a communication frequency band.

First and second paths (I,II) are connected in parallel between an input terminal (IN) and an output terminal (OUT). A high-pass filter (HPF) is provided in the first path (I). A low-pass filter (LPF) is provided in the second path (II). A switch (SW1-SW4) connects one of the high-pass filter (HPF) and the low-pass filter (LPF) to the input terminal (IN) and the output terminal (OUT) and disconnects the other. A transmission line (TL1,TL2) is provided on the first and second paths (I,II) respectively. A line length of the transmission line (TL1,TL2) is adjusted such that a resonance caused due to circuit constants of the high-pass filter (HPF) and the low-pass filter (LPF) and capacitance obtained when the switch (SW1-SW4) is OFF is shifted to a communication frequency band.

A switch device is disclosed. The switch device includes: an input point; a first output point; a second output point; a first transmission line connecting the input point to the first output point; a second transmission line connecting the input point to the second output point; a switch unit connected to the first output point; and a third transmission line of which one end is connected to the switch unit and the other end is connected to the second output point, wherein the third transmission line causes a 90-degree phase shift when a signal at an operating frequency is delivered therethrough, the switch unit is controlled to be in an ON or OFF state according to one control signal, opens or grounds each of the first output point and the one end of the third transmission line.

A switch device is disclosed. The switch device includes: an input point; a first output point; a second output point; a first transmission line connecting the input point to the first output point; a second transmission line connecting the input point to the second output point; a switch unit connected to the first output point; and a third transmission line of which one end is connected to the switch unit and the other end is connected to the second output point, wherein the third transmission line causes a 90-degree phase shift when a signal at an operating frequency is delivered therethrough, the switch unit is controlled to be in an ON or OFF state according to one control signal, opens or grounds each of the first output point and the one end of the third transmission line.

An apparatus is disclosed for phase-shifting signals. In example implementations, the apparatus includes a phase shifter. The phase shifter includes a first port, a second port, a vector modulator coupled to the first port, and a signal phase generator. The signal phase generator includes multiple amplifiers coupled between the vector modulator and the second port. The signal phase generator also includes multiple capacitors that couple the multiple amplifiers together to form a loop. Each respective capacitor of the multiple capacitors is coupled between a respective pair of consecutive amplifiers of the multiple amplifiers to form the loop.