The present disclosure provides a voltage variable attenuator (VVA) with a controllable matching network. The output of the attenuation portion of the VVA is couple to a matching network. The matching network includes a resistive element, which may be a Field Effect Transistor (FET), whose resistance may be controlled as a function of attenuation. In particular, a control voltage used to control the resistance of the attenuation portion of the VVA is also used to control the resistive element of the matching network. In this manner, the output impedance of the VVA may be maintained at a desired level.

A circuit for attenuating a signal has an input configured to receive an input signal, an output configured to transmit an output signal, a first attenuation path (having a first active circuit device) between the input and the output, and a second attenuation path between the input and the output. The circuit also has an operational amplifier that, like most operational amplifiers, has a first op-amp input, a second op-amp input, and an op-amp output. In addition, the circuit has a voltage control device coupled with the first op-amp input, and a second active circuit device having a first active terminal coupled with the second op-amp input. A feedback loop is coupled between the op-amp output and a second active terminal of the second active circuit device. Moreover, the op-amp output also is coupled with the first active circuit device.

Methods and devices to reduce glitches in phase shifters implementing high isolation switches are disclosed. Such glitches occur at the output of the phase shifters when transitioning from one phase shift to another. The disclosed method implements delays in various steps of the phase shifter transitions. Exemplary embodiments implementing single-pole multi-throw are provided and exemplary performance of the disclosed methods are also presented. The described methods are also applicable to multi-step attenuators.

A high frequency variable attenuation circuit includes an input terminal, an output terminal, a first resistor, a second resistor, a third resistor, and a first switching circuit. The first switching circuit has an output side resistor and an output side switching element that are connected in series to each other. The first switching circuit has a first circuit end connected to the second end of the second resistor and the output terminal, and a second circuit end connected to the ground.

A method for improving the stability and reducing phase variations of an ultra-wideband attenuator, with respect to temperature variations, comprising the steps of providing an attenuator implemented in ?-topology and consisting of a serial path between the input and the output of the attenuator, including a first serial resistor Rs.sub.1 connected to the input, followed by a serial inductor Ls, followed by a second serial resistor Rs.sub.2 connected to the output; a first transistor T.sub.1 bridging between the input and the output, for controlling the impedance of the serial path by a first control input provided to the first transistor T.sub.1; a first parallel path between the input and ground, including a first parallel transistor T.sub.2a followed by first parallel resistor Rp.sub.1; a second parallel path between the output and ground, including a second parallel transistor T.sub.2b followed by second parallel resistor Rp.sub.2; a second control input commonly provided to first parallel transistor T.sub.2a and to the second parallel transistor T.sub.2b, for controlling the impedance of the first and second parallel paths; unifying the serial resistors to a common serial resistor Rs and splitting the serial inductor Ls to two serial inductors Ls.sub.1 and Ls.sub.2, such that one serial inductor is connected between the input and a first contract of the common serial resistor Rs and the other serial inductor is connected between the output and the other contact of the common serial resistor Rs; splitting the parallel resistor Rp.sub.1 to two smaller resistors, connecting a first smaller resistor to the input, connecting a second smaller resistor to the first smaller resistor via the first parallel transistor T.sub.2a and to ground via a third parallel transistor T.sub.3a; splitting the parallel resistor Rp.sub.2 to two smaller resistors, connecting a third smaller resistor to the output, connecting a fourth smaller resistor to the third smaller resistor via the second parallel transistor T.sub.2b and to ground via a fourth parallel transistor T.sub.3b; connecting a first feedback capacitor Cfb.sub.1 between the common point connecting between the ungrounded port of the second parallel transistor T.sub.3a and the first contract of the common serial resistor Rs and connecting a second feedback capacitor Cfb.sub.2 between the common point connecting between the ungrounded port of the fourth parallel transistor T.sub.3b and the second contract of the common serial resistor Rs; upon controlling the first and second parallel transistors T.sub.2a and T.sub.2b by the second control input, simultaneously controlling also the third and the fourth parallel trans

Circuits and methods for eliminating or mitigating the amount of temperature-dependent variation in the relative attenuation of a multi-valued digital step attenuator (DSA) by using resistive components having temperature-dependent resistance values that compensate for or offset changes in the temperature-dependent ON resistance (R.sub.ON) of the switches within the DSA. In some embodiments, DSA attenuator cell switches are fabricated to have positive first-order resistance temperature (FORT) coefficients, while temperature-compensating series attenuation resistances are fabricated as a positive FORT coefficient resistor and temperature-compensating shunt resistances are fabricated as either a negative FORT coefficient resistor or a combination of a negative FORT coefficient resistor in parallel with a positive FORT coefficient resistor.

An apparatus includes a radio frequency (RF) input port, an RF output port, a variable attenuation network, a first filter network, a second filter network, and a third filter network. The variable attenuation network may be coupled between the RF input port and the RF output port. Attenuation of the variable attenuation network is controlled by a first control signal and a second control signal. The first filter network may be connected between the RF input port and the RF output port. The second filter network may be connected between the variable attenuation network and a ground potential. The third filter network may be connected between the variable attenuation network and the ground potential. The first, the second, and the third filter networks modify performance of the variable attenuation network to produce a particular tilt of a radio frequency signal passing through the apparatus between the RF input port and the RF output port. The particular tilt is selectable by adjustment of at least one of the first and the second control signals.

A variable attenuator (v-ATT) is disclosed. The v-ATT includes an input terminal, an output terminal, a transmission line between the input and output terminals, at least two stages provided between the transmission line and the ground, and a bias unit. Each of the stages includes a field effect transistor (FET) that varies impedance between the transmission line and the ground according to a bias provided to the gate thereof. The bias unit generates the biases each provided to the stages. One of the features of the v-ATT is that at least one of the stages receives at least one of the biases that is different from biases provided to other of the at least one of the stages.

Apparatus and methods for digital step attenuators are provided herein. In certain configurations, a DSA includes a plurality of DSA stages that can be set in an attenuation mode or in a bypass mode using a plurality of switching circuits. A first switching circuit of the plurality of switching circuits includes a field effect transistor (FET) switch, a gate resistor, one or more gate resistor bypass switches, and a pulse generation circuit. The gate resistor is electrically connected between a switch control input and a gate of the FET switch, and a switch control signal can be provided to the switch control input to turn on or off the FET switch. In response to detecting a rising and/or falling edge of the switch control signal, the pulse generation circuit can control the one or more gate resistor bypass switches to bypass the gate resistor.

A self-matching phase shifter/attenuator including several incremental impedance matched phase shifter/attenuator elements is disclosed. Each incremental impedance matched phase shifter element comprises a reactive component (such as either a capacitor or inductor) that can be coupled in shunt to the signal path. The shunt reactive component is coupled in series with a ground switch. When closed, the ground switch connects the shunt reactive component to ground. When the ground switch is open, the switch removes the shunt reactive component from the circuit. In addition, each incremental impedance matched phase shifter element comprises a series reactive component having a reactance that is typically equal and inverse of that of the shunt reactive component.