The disclosure provides an RF receiver. The RF receiver includes an input driver. The input driver receives a coarse signal, and generates an input signal. A digital step attenuator (DSA) is coupled to the input driver and receives the input signal. An analog to digital converter (ADC) is coupled to the DSA. The DSA includes a serial capacitor coupled to the input driver. The DSA also includes a sampling capacitor coupled to the ADC.

A computing cable comprising a trace having a first impedance and an attenuator that includes a fixed resistor having a second resistance, a variable resistor having a first resistance, and a conductor having a second impedance. The combination of the first resistance, the second resistance, and the second impedance is based on the first impedance, wherein the first resistance is varied dynamically at runtime based on a control input.

A memory device includes an array of memory cells, a diode having a threshold voltage that changes with temperature, an analog-to-digital converter (ADC), and a pulse generator. The ADC includes a voltage comparator having a positive terminal coupled with the diode. The ADC further includes a first capacitor coupled between a negative terminal of the voltage comparator and ground, and a second capacitor selectively coupled between the first capacitor and a voltage reference node. The second capacitor has a smaller capacitance than that of the first capacitor. The pulse generator is coupled with the ADC and generates pulses. The pulses cause the first capacitor to connect to the second capacitor and equalize charge between the first capacitor and the second capacitor. An inverted signal of the pulses causes the second capacitor to be coupled with the voltage reference node to pre-charge the first capacitor.

An attenuator system comprising a variable impedance configured to provide an impedance from among a plurality of impedance states, the variable impedance comprising a first port, a second port, a first transistor comprising first and second channel terminals coupled between the first port and the second port, and a second transistor comprising first and second channel terminals coupled between the first port and the second port, and a control circuit configured to control the variable impedance to a first impedance state of the plurality of impedance states at least in part by providing a first output voltage to a control terminal of the first transistor to turn the first transistor on, wherein the first transistor is configured to operate in an under-driven mode when turned on.

A ringing suppressor circuit is connected to a differential signal transmission line that includes a high potential signal line and low potential signal line pair for transmitting high and low level differential signals, and includes a ringing suppressor and a stopper. When the differential signal changes to a high level, the ringing suppressor suppresses ringing by lowering the impedance between the signal lines by turning ON of a switching element. When a differential signal voltage drops below a voltage lowering determination voltage, the stopper stops the impedance lowering function of the ringing suppressor by turning OFF another switching element.

A control circuit is disclosed for controlling operation of a radio frequency (RF) transistor. The control circuit has a first sub-circuit that accepts a reference voltage and a reference current. The control circuit has a second sub-circuit with a plurality of stacked transistors coupled between the first sub-circuit and ground, and a resistor ladder coupled between the first sub-circuit and an output port of the control circuit. The first sub-circuit provides the reference current to flow through the stacked transistors, and sets a total voltage drop across the stacked transistors equal to the reference voltage. The first sub-circuit also sets a total voltage drop across the resistor ladder equal to the reference voltage. Each rung of the resistor ladder is coupled to control an operating voltage of a stacked transistor, to cause each stacked transistor to operate with similar control conditions.

An attenuator for attenuating a signal is disclosed. The attenuator comprises a differential input port with a positive input node and a negative input node to receive the signal; and a differential output port with a positive output node and a negative output node to output the attenuated signal. The attenuator further comprises a first switched resistor network connected between the positive input node and the positive output node; and a second switched resistor network connected between the negative input node and the negative output node. Further a pair of compensation paths is connected to the first and second switched resistor networks for cancellation their parasitic leakages, where a first compensation path is connected between the positive input node and the negative output node, and a second compensation path is connected between the negative input node and the positive output node. The attenuator further comprises a control circuit to generate control signals for controlling the first and second switched resistor networks.

A variable attenuator operable in a frequency band from at least to 10 GHz is disclosed. The variable attenuator includes an input port; an output port; a first transmission line connecting the input port with the output port; an attenuating unit provided between the first transmission line and the ground; and a second transmission line. The attenuating unit includes at least one transistor with two current terminals coupled with the first transmission line and the ground, respectively. The second transmission line coupled between the two current terminals of the transistor. The second transmission line is operable as an inductor in the frequency band. A feature of the variable attenuator, the transistor and the second transmission line cause a resonance frequency within the frequency band by a capacitor attributed between the two current terminals and the inductance of the second transmission line.

A computing cable comprising a trace having a first impedance and an attenuator that includes a fixed resistor having a second resistance, a variable resistor having a first resistance, and a conductor having a second impedance. The combination of the first resistance, the second resistance, and the second impedance is based on the first impedance, wherein the first resistance is varied dynamically at runtime based on a control input.

An electronic circuit configured to present a high-impedance load between a load point and a reference point includes a capacitive element (C) provided between a first node (Node A) and the reference point, a first element (D.sub.1) connected in parallel with the capacitive element (C), a first switching element (S.sub.1) provided in series between the first node (A) and a voltage source point, a second switching element (S.sub.2) provided between the first node (A) and a second node (Node B), a second element (D.sub.2) connected between the second switching element (S.sub.2), the load point, and the reference point, and timing control logic configured to implement three stages. In a charging stage, the first switching element (S.sub.1) is closed and the second switching element (S.sub.2) to charge a nodal voltage v.sub.D(t) at the first node (A). In discharge stage, the first switching element (S.sub.1) is open and the second switching element (S.sub.2) is open to enable discharging of the capacitive element (C) through the first element (D.sub.1). In a transfer stage, the second switching element (S.sub.2) is closed to connect the first node (A) and the second node (B), after which the second switching element (S.sub.2) is opened and the second element (D.sub.2) is biased to present the high-impedance load.