Certain aspects of the present disclosure relate to multi-band filter architectures and methods for filtering signals using the multi-band filter architectures. One example multi-band filter generally includes a transconductance-capacitance (gm-C) filter and a reconfigurable load impedance coupled to an output of the gm-C filter, the reconfigurable load impedance comprising a first gyrator circuit coupled to a second gyrator circuit.

Certain aspects of the present disclosure provide an N-path filter implemented using a generalized impedance converter (GIC) circuit. The GIC circuit is configured such that the N-path filter has a desired frequency response, which may include a wide passband with steeper rejection than a conventional N-path filter with only a single pole in each filter path. Certain aspects of the present disclosure provide an N-path filter having a frequency response with multiple concurrent passbands. In certain aspects, the N-path filter with multiple passbands is implemented using the GIC circuit. In other aspects, the N-path filter may include a bandpass response circuit where an inductance of the bandpass response circuit may be implemented using gyrators.

[Object] To propose a wireless communication apparatus capable of realizing separation of transmission signals and reception signals with a low power consumption and a small size. [Solution] Provided is a wireless communication apparatus including: a gyrator that includes at least four terminals; a single-phase differential converter that mutually converts single-phase signals and differential signals; a low-noise differential amplifier that amplifies reception signals that the gyrator outputs; and a differential power amplifier that amplifies transmission signals to be output to the gyrator. The gyrator transmits signals from a first terminal and a second terminal in the direction of a third terminal and a fourth terminal. Any of the single-phase differential converter, the low-noise amplifier, and the power amplifier are connected to the first terminal and second terminal, the third terminal and fourth terminal, the first terminal and third terminal, and the second terminal and fourth terminal of the gyrator.

[Object] To propose a wireless communication apparatus capable of realizing separation of transmission signals and reception signals with a low power consumption and a small size. [Solution] Provided is a wireless communication apparatus including: a gyrator that includes at least four terminals; a single-phase differential converter that mutually converts single-phase signals and differential signals; a low-noise differential amplifier that amplifies reception signals that the gyrator outputs; and a differential power amplifier that amplifies transmission signals to be output to the gyrator. The gyrator transmits signals from a first terminal and a second terminal in the direction of a third terminal and a fourth terminal. Any of the single-phase differential converter, the low-noise amplifier, and the power amplifier are connected to the first terminal and second terminal, the third terminal and fourth terminal, the first terminal and third terminal, and the second terminal and fourth terminal of the gyrator.

An aspect relates to a filter or a first gyrator including a first set of cascaded inverters, and a first set of one or more passive devices coupled to the first set of cascaded inverters. Another aspect relates to a method including applying an input signal to an input of a first one of a set of cascaded inverters coupled to a set of one or more passive devices, and receiving an output signal from the set of cascaded inverters, the output signal being a filtered version of the input signal. Still another aspect relates to a transceiver including a filter with a first set of cascaded inverters, and a first set of one or more passive devices coupled to the first set of cascaded inverters; and a mixer coupled to the filter.

A high peak bandwidth I/O channel embedded within a multilayer surface interface that forms the bus circuitry electrically interfacing the output or input port on a first semiconductor die with the input or output port on a second semiconductor die.

A high peak bandwidth I/O channel embedded within a multilayer surface interface that forms the bus circuitry electrically interfacing the output or input port on a first semiconductor die with the input or output port on a second semiconductor die.

Design and construction of high interconnection density, minimal loss I/O channels comprising embedded passive networks that preserve signal integrity at signaling frequencies above 1 GHz, preferably above 10 GHz, to improve memory-processor bandwidths.

Design and construction of high interconnection density, minimal loss I/O channels comprising embedded passive networks that preserve signal integrity at signaling frequencies above 1 GHz, preferably above 10 GHz, to improve memory-processor bandwidths.