A circuit and method are provided. The method couples a first bias signal to a first internal node and a second internal node via a first resistor and a second resistor, respectively, couples a second bias signal to a third internal node and a fourth internal node via a third resistor and a fourth resistor, respectively. The method further couples the first internal node to the second internal node via a switch of a first type controlled by a first control signal, couples the third internal node to the fourth internal node via a switch of a second type controlled by a second control signal, wherein the second control signal is an inversion of the first control signal, couples a first terminal to the first internal node and the third internal node via a first capacitor and a third capacitor, respectively; and couples a second terminal to the second internal node and the fourth internal node via a second capacitor and a fourth capacitor, respectively.

A circuit and method are provided. The method couples a first bias signal to a first internal node via a first resistor, couples a second bias signal to a second internal node via a second resistor, couples the first internal node to a ground node via a N-type switch, couples the second internal node to a power supply node via a P-type switch. The method further couples the first internal node to the second internal node via a transmission gate, couples a terminal to the first internal node via a first capacitor, and couples the terminal to the second internal node via a second capacitor.

A circuit and method are provided. The method couples a first bias signal to a first internal node and a second internal node via a first resistor and a second resistor, respectively, couples a second bias signal to a third internal node and a fourth internal node via a third resistor and a fourth resistor, respectively. The method further couples the first internal node to the second internal node via a switch of a first type controlled by a first control signal, couples the third internal node to the fourth internal node via a switch of a second type controlled by a second control signal, wherein the second control signal is an inversion of the first control signal, couples a first terminal to the first internal node and the third internal node via a first capacitor and a third capacitor, respectively; and couples a second terminal to the second internal node and the fourth internal node via a second capacitor and a fourth capacitor, respectively.

An apparatus has advanced amplifier Classes and low pass filter technologies for using software generated ascending or level waveforms that are effective when applying cardiac defibrillation and cardioversion waveforms which significantly reduce damage to the heart muscle. The apparatus comprises a waveform energy control system for delivering software generated waveforms comprising differentially driven Class D and Class B amplifier sections, wherein the Class D amplifier section produces Phase 1 ascending waveforms and has a programmable lowpass filter (LPF) and wherein the Class B amplifier section delivers hard-switched Phase 2 waveforms.

A circuit and method are provided. The method couples a first bias signal to a first internal node via a first resistor, couples a second bias signal to a second internal node via a second resistor, couples the first internal node to a ground node via a N-type switch.sub.; couples the second internal node to a power supply node via a P-type switch. The method further couples the first internal node to the second internal node via a transmission gate, couples a terminal to the first internal node via a first capacitor, and couples the terminal to the second internal node via a second capacitor.

An apparatus has advanced amplifier Classes and low pass filter technologies for using software generated ascending or level waveforms that are effective when applying cardiac defibrillation and cardioversion waveforms which significantly reduce damage to the heart muscle. The apparatus comprises a waveform energy control system for delivering software generated waveforms comprising differentially driven Class D and Class B amplifier sections, wherein the Class D amplifier section produces Phase 1 ascending waveforms and has a programmable lowpass filter (LPF) and wherein the Class B amplifier section delivers hard-switched Phase 2 waveforms.

A circuit comprises a first amplifier coupled to a first and a second node; a differential capacitive load coupled to the first and the second node, the differential capacitive load coupled between drains of transistors in a cross coupled transistor circuit; a current mirror coupled to a source of each transistor; and a capacitor coupled between the sources of the transistors. A plurality of amplifiers can be coupled to the differential capacitive load, wherein each amplifier comprises a clock-less pre-amplifier of a comparator. The amplifiers may be abutted to one another such that an active transistor of a first differential stage in a first amplifier behaves as a dummy transistor for an adjacent differential stage in a second amplifier.

A capacitor bank has a capacitance value that is discontinuous and has an extremely narrow variable range. Thus, in a case of obtaining a wide variable range of the capacitance value, a large number of capacitors are connected in parallel and used while being switched by switches. The present technology achieves at least one of: allowing the capacitance value of a variable capacitance circuit to be varied continuously by electrical control without increasing the parasitic capacitance; and decreasing the current consumption of an oscillator circuit using the variable capacitance circuit as compared to a conventional case. The variable capacitance circuit includes: a transconductance circuit that includes a MOS transistor; an inductor that is connected in parallel to the transconductance circuit; and a Gm control circuit that varies a transconductance of the MOS transistor.

A method couples a first bias signal to first and second internal nodes via first and second resistors, couples a second bias signal to third and fourth internal nodes via third and fourth resistors, couples the first internal node to the second internal node via a switch of a first type, and couples the third internal node to the fourth internal node via a switch of a second type. The method further couples the first internal node to the third internal node via a first transmission gate, couples the second internal node to the fourth internal node via a second transmission gate, couples a first terminal to the first and third internal nodes via first and third capacitors, respectively, and couples a second terminal to the second and fourth internal nodes via second and fourth capacitors, respectively.

A tunable impedance simulator and impedance multiplier circuit and a system for configuring a second generation voltage-mode conveyor circuit (VCII) as the tunable impedance simulator and impedance multiplier are described. The tunable impedance simulator and impedance multiplier circuit includes one VCII having a positive input terminal connected to a voltage source, a negative input terminal connected to the voltage source, and an impedance terminal Z.sub.0 . The impedance terminal Z.sub.0 can be either positive or negative. When the impedance terminal Z.sub.0 is positive, a positive active inductor, a positive capacitance multiplier, and a positive resistance multiplier may be implemented. When the impedance terminal Z.sub.0 is negative, a negative active inductor, a negative capacitance simulator, and a negative resistance simulator may be implemented.