Methods and apparatus are provided for adapting gain elements in digital filter chains. In one example, a digital filter chain includes a first digital filter and a second digital filter having an input coupled to an output of the first digital filter. A common gain is applied to signal samples passing between the first digital filter and the second digital filter, the common gain corresponding to a product of an output gain associated with the first digital filter and an input gain associated with the second digital filter. In another example, a digital filter includes an adjustable input gain element and an adjustable output gain element. The adjustable input gain element is configured to apply a gain value to an input signal sample, the gain value comprising a resultant difference of a bitshift configured for the digital filter and a bitwidth extension value. The adjustable output gain element is configured to apply an opposite of the gain value to an output signal sample.

Systems and methods are provided in which a wireless receiver can be configured to digitally synchronize a receive sampling rate to a transmit sampling rate, and may include a digital interpolator controlled by a timing control unit with a timing offset estimator. The timing control unit can be configured to calculate and output parameters to the digital interpolator. The digital interpolator can include a sample buffer followed by a fractional delay filter. Output parameters to the digital interpolator can include a fractional delay timing offset signal of the receiver relative to a transmitter timing signal and a buffer pointer control signal to control a position of the read pointer relative to a write pointer to compensate for subsample timing offset. The timing offset estimator can be configured to calculate and provide to the timing control unit a sampling period ratio control word and an instantaneous timing offset control word.

An FIR filter convolutes sampled data obtained by sampling a reception signal with tap coefficients. A phase difference detector detects a phase difference between a synchronization timing of a signal waveform estimated from an output signal of the FIR filter and a sampling timing of the output signal. A tap coefficient adjuster adjusts the tap coefficients so as to reduce the phase difference detected by the phase difference detector and causes the sampling timing of the output signal of the FIR filter to track the synchronization timing.

The disclosed electrosurgical systems and methods accurately determine the power actually applied to a load by using equalizers to calibrate the power measurements. The electrosurgical systems include an electrosurgical generator and an electrosurgical instrument coupled to the electrosurgical generator through an electrosurgical cable. The electrosurgical generator includes an electrical energy source, voltage and current detectors, equalizers that estimate the voltage and current applied to a load, and a power calculation unit that calculates estimated power based upon the estimated voltage and current. The methods of calibrating an electrosurgical generator involve applying a resistive element across output terminals of the electrosurgical generator, applying a test signal to the resistive element, measuring the magnitude and phase angle of voltage and current components of the test signal within the electrosurgical generator, estimating the magnitude and phase angle of the voltage and current at the resistive element using equalizers, and determining gain correction factors and minimum phase angles for the equalizers.

Methods and apparatus are provided for adapting gain elements in digital filter chains. In one example, a digital filter chain includes a first digital filter and a second digital filter having an input coupled to an output of the first digital filter. A common gain is applied to signal samples passing between the first digital filter and the second digital filter, the common gain corresponding to a product of an output gain associated with the first digital filter and an input gain associated with the second digital filter. In another example, a digital filter includes an adjustable input gain element and an adjustable output gain element. The adjustable input gain element is configured to apply a gain value to an input signal sample, the gain value comprising a resultant difference of a bitshift configured for the digital filter and a bitwidth extension value. The adjustable output gain element is configured to apply an opposite of the gain value to an output signal sample.

A processing element for implementation in a digital signal processing system is provided. The processing element is configured to receive a first data stream comprising a plurality of digital values where each value represents a sample of an analog signal. The processing element is further configured to receive a second data stream comprising a series of digital values where each value represents a sample of the analog signal. The processing element is configured to filter the first data stream via a first Farrow-structured fractional delay (FD) filter and output a filtered first data stream; filter the second data stream via a second Farrow-structured FD filter and output a filtered second data stream; and temporarily store values from the second data stream and output the stored values to the first Farrow-structured FD filter so that the stored values can be used to filter the first data stream.

Methods and apparatus are provided for adapting gain elements in digital filter chains. In one example, a digital filter chain includes a first digital filter and a second digital filter. The first digital filter includes a fixed point finite impulse response (FIR) filter and includes an output gain element. The second digital filter has an input coupled to an output of the first digital filter and includes an IIR filter. The output gain element applies a common output gain value that is based on a product of an input gain configured in association with the second digital filter and an FIR output gain that is based on a scaling factor K associated with the first digital filter.

Aspects of this disclosure relate to an asynchronous sample rate converter (ASRC) comprising a signal input configured to receive an input signal having one or more input signal values at a first sample rate, a first clock input configured to receive an input clock signal corresponding to the first sample rate, a signal output configured to provide an output signal having one or more output signal values at a second sample rate, a second clock input configured to receive an output clock signal corresponding to the second sample rate, a zero-padding circuit configured to add a plurality of zero values following at least one of the one or more input signal values, and a filter configured to generate the output signal, the output signal having one or more output signal values based on the input signal.