An apparatus for modifying a sampling rate includes a forward transformer for forming a first version of a spectrogram by means of transformation with a first transformation length from an information signal with a first sampling rate. The apparatus includes a processor for forming a second version of the spectrogram with a lower bandwidth than the first version. The apparatus includes a reverse transformer for forming a coarsely pre-modified information signal with a second sampling rate that is reduced with respect to the first sampling rate, by means of reverse transformation of the second version of the spectrogram with a second transformation length that is reduced with respect to the first transformation length. The apparatus includes a time domain interpolator for acquiring an information signal with a third sampling rate that is modified with respect to the second sampling rate, by means of interpolation of the pre-modified information signal.

A method for optimizing processor operation in a processing system including one or more digital filters is provided according to the invention. The method includes generating initial filter coefficients for the one or more digital filters of the processing system, determining one or more initial filter coefficients for at least one digital filter of the one or more digital filters that can be dropped and dropping the one or more initial filter coefficients. Dropping the one or more initial filter coefficients reduces a total number of filter coefficients to be used by the processing system.

In order to enhance the speed of a processing necessary for setting the factor of a filter and further maintain the accuracy of the filter, a digital processing apparatus includes: a Fourier transform unit that Fourier transforms a time domain digital signal, thereby generating N frequency domain signals; a filter unit that uses N first factors to process the frequency domain signals in the frequency domain; an inverse Fourier transform unit that transforms the frequency domain signals as processed by the filer unit to a time domain digital signal; a low accuracy factor calculation unit that uses m second factors to calculate N first A factors; a high accuracy factor calculation unit that includes a factor division unit for calculating respective ratios of N third factors to the N first A factors and that also includes a factor variable unit for calculating N first B factors varying stepwise from one to the respective ratios; a multiplication unit that multiplies the first A factors by the first B factors, thereby calculating the N first factors; and a control unit that controls the low accuracy factor calculation unit and high accuracy factor calculation unit by causing only the low accuracy factor calculation unit to operate with the first B factors being set to one and thereafter causing the high accuracy factor calculation unit to calculate the first B factors based on the third factors.

The proposed dynamic current-mode finite impulse response (FIR) filter includes a coefficient signal generator to generate a coefficient signal, an input signal generator to generate an input signal, a dynamic current multiplier configured to receive the input signal and the coefficient signal and to generate intermediate product terms that are multiplications of the coefficient values and reflected and shifted input values, and an accumulator configured to receive the intermediate product terms and to sequentially integrate the intermediate product terms over the coefficient values to produce output responses for the input values. The dynamic current multiplier includes a first dynamically configured transistor (DCT) having a first input node to receive the first input signal during a first phase of operation and a second input node to receive the second input signal during a second phase of operation, and a second DCT having an input node to receive a third input signal during a first phase of operation, and output the intermediate product terms during a second phase of operation.

The proposed dynamic current-mode finite impulse response (FIR) filter includes a coefficient signal generator to generate a coefficient signal, an input signal generator to generate an input signal, a dynamic current multiplier configured to receive the input signal and the coefficient signal and to generate intermediate product terms that are multiplications of the coefficient values and reflected and shifted input values, and an accumulator configured to receive the intermediate product terms and to sequentially integrate the intermediate product terms over the coefficient values to produce output responses for the input values. The dynamic current multiplier includes a first dynamically configured transistor (DCT) having a first input node to receive the first input signal during a first phase of operation and a second input node to receive the second input signal during a second phase of operation, and a second DCT having an input node to receive a third input signal during a first phase of operation, and output the intermediate product terms during a second phase of operation.

The present disclosure provides implementations of a filter suitable for use in quantum computing systems and other low-power, high-speed applications. In some aspects, a filter circuit includes a series-connected arrangement of unit delays and summers in an alternating pattern. The filter circuit further includes a plurality of coefficient multipliers, each having a respective output connected with one or more of the summers, and each including a multiplexing stage including one or more multiplexers addressed using one or more bits of a respective input coefficient vector. A first coefficient multiplier of the plurality of coefficient multipliers includes a partial product stage configured to provide a plurality of integer partial products of an input data vector to the multiplexing stages of the plurality of coefficient multipliers.

The present disclosure provides implementations of a filter suitable for use in quantum computing systems and other low-power, high-speed applications. In some aspects, a filter circuit includes a series-connected arrangement of unit delays and summers in an alternating pattern. The filter circuit further includes a plurality of coefficient multipliers, each having a respective output connected with one or more of the summers, and each including a multiplexing stage including one or more multiplexers addressed using one or more bits of a respective input coefficient vector. A first coefficient multiplier of the plurality of coefficient multipliers includes a partial product stage configured to provide a plurality of integer partial products of an input data vector to the multiplexing stages of the plurality of coefficient multipliers.