Various embodiments are generally directed to techniques for optimizing convolution filters. Generally, embodiments may determine, based on an analysis of a plurality of values of a convolution filter, an optimization operation to optimize at least one value of the plurality of values of the convolution filter. Embodiments may perform the optimization operation on the values of the convolution filter to generate an optimized convolution filter. Embodiments may also perform a convolution operation by a convolution logic based on the optimized convolution filter and an input data.

The invention relates to a method for filtering a numerical input signal sampled at a sampling frequency in order to obtain a filtered signal, the method being performed by a radar system and including at least one step for obtaining a first (respectively second) output signal by carrying out first (respectively second) operations on the first (respectively second) processing channel, the first (respectively second) operations including at least the application of a discrete Fourier transform to M/2 points on a signal coming from the input signal, and applying an inverse discrete Fourier transform to M/2 points on the first signal in order to obtain M points of the spectrum of the first signal, M being an integer strictly greater than 2, the application step being carried out by the addition of the results of two processing channels.

A finite impulse response (FIR) filter circuit design method using approximate computing, the FIR filter circuit design method including: replacing adders of the FIR filter with approximate adders; and performing a synthesis work according to a set approximate synthesis flow when the replacing of the adders of the FIR filter are replaced with the approximate adders is performed, wherein, in the approximate synthesis flow, a numeric column of each of the approximate adders is divided into an accurate part and an inaccurate part, and a numeric column of the inaccurate part is approximated. In the FIR filter, conventional adders/subtractors are replaced with addition/subtraction having an automated synthesis flow so that energy consumption can be reduced.