A Scalable Finite Impulse Response (SFIR) filter includes a pre-processing section, a post-processing section, and a finite impulse response (FIR) Matrix. The FIR Matrix is coupled to the pre-processing section and the post-processing section. The FIR Matrix includes a plurality of filter taps and a plurality of signal paths. Each filter tap of the plurality of filter taps has at least a first input, a second input, a multiplexer coupled to the first input and the second input, and a first flip-flop coupled to an output of the multiplexer. The plurality of signal paths are arranged to allow re-configurable data throughput between the each filter tap of the plurality of filter taps.

The invention relates to a method (100) for switching between desired value filters (26, 28) of a drive means (52) for a machine axis (10, 12) during operation. An input signal (20) is applied to the first and to the second desired value filter (26, 28) for producing a first and a second output signal (23, 33). Then any deviation between the first and the second output signal (23, 33) is determined. If the deviation falls below a threshold value, the first desired value filter (26) is separated from the drive means (52) and substantially simultaneously the second desired value filter (28) is connected to the drive means (52). The desired value filters (26, 28) have different running times (19).

Various embodiments relate to delta-sigma loop filters with input feedforward. A delta-sigma loop filter may include a first integrator and a quantizer having an input coupled to an output of the first integrator. The delta-sigma loop filter may further include a first summing node having an output coupled to an input of the first integrator. Further, the delta-sigma loop filter may include a feedforward path from an input of the delta-sigma loop filter to a first input of the first summing node. The delta-sigma loop filter may also include a first feedback path from an output of the quantizer to a second input of the first summing node.

Various embodiments relate to an analog-to-digital converter (ADC). The ADC may include a first channel including a first delta-sigma loop filter and a second channel including a second delta-sigma loop filter. Each of the first delta-sigma loop filter and the second delta-sigma loop filter may include a first integrator and a quantizer having an input coupled to an output of the first integrator. Each of the first delta-sigma loop filter and the second delta-sigma loop filter may also include a first summing node having an output coupled to an input of the first integrator, and a feedforward path from an input of the delta-signal loop filter to a first input of the first summing node. Further, each of the first delta-sigma loop filter and the second delta-sigma loop filter may include a first feedback path from an output of the quantizer to a second input of the first summing node.

A Scalable Finite Impulse Response (SFIR) filter is disclosed. The SFIR filter includes a pre-processing section, a post-processing section, and a finite impulse response (FIR) Matrix. The FIR Matrix includes a plurality of filter taps and a plurality of signal paths in signal communication with each filter tap. The plurality of signal paths are arranged to allow re-configurable data throughput between the each filter tap and the pre-processing section and post-processing section are in signal communication with the FIR Matrix.

In some embodiments, a multiplier-based programmable filter comprises a pre-scaling circuit, a first multiplier circuit coupled to a first output of the pre-scaling circuit and a second output of the pre-scaling circuit, and a second multiplier circuit coupled to the first output of the pre-scaling circuit and the second output of the pre-scaling circuit. In some embodiments, the multiplier-based programmable filter also comprises a first adder coupled to a first output of the first multiplier circuit and a second output of the first multiplier circuit, a second adder coupled to a first output of the second multiplier circuit and a second output of the second multiplier circuit, first register coupled to an output of the first adder and an input of the second adder, and a second register coupled to an output of the second adder.

When an instruction is provided for changing a characteristic of a set filter which includes a plurality of partial filters and forms a specified characteristic by combining a plurality of partial filters, a processor performs, as crossfading processing for a first filter and a second filter among the plurality of partial filters, fade-out processing of gradually decreasing a degree of contribution of the first filter to the characteristic and fade-in processing of gradually increasing a degree of contribution of the second filter to the characteristic. As a result, unnaturalness occurring at the time of changing filter characteristics is solved.

In some embodiments, a multiplier-based programmable filter comprises a pre-scaling circuit, a first multiplier circuit coupled to a first output of the pre-scaling circuit and a second output of the pre-scaling circuit, and a second multiplier circuit coupled to the first output of the pre-scaling circuit and the second output of the pre-scaling circuit. In some embodiments, the multiplier-based programmable filter also comprises a first adder coupled to a first output of the first multiplier circuit and a second output of the first multiplier circuit, a second adder coupled to a first output of the second multiplier circuit and a second output of the second multiplier circuit, first register coupled to an output of the first adder and an input of the second adder, and a second register coupled to an output of the second adder.

Methods and devices for switching filters and medical apparatuses using the same are described. The method includes: detecting whether or not a frequency range of an input signal is changed from a first frequency range into a second frequency range; if changed, switching from a first filter to a second filter, and taking a sample value of the input signal at a current moment as an input value of the second filter at the current moment and sample values of the input signal at n moments before the current moment as input values of the second filter at the n moments, respectively, and taking output values of the first filter at m moments before the current moment as output values of the second filter at the m moments, to obtain an output value of the second filter at the current moment.

When an instruction is provided for changing a characteristic of a set filter which includes a plurality of partial filters and forms a specified characteristic by combining a plurality of partial filters, a processor performs, as crossfading processing for a first filter and a second filter among the plurality of partial filters, fade-out processing of gradually decreasing a degree of contribution of the first filter to the characteristic and fade-in processing of gradually increasing a degree of contribution of the second filter to the characteristic. As a result, unnaturalness occurring at the time of changing filter characteristics is solved.