A position coordinate difference computing unit (5a to 5c) calculates position coordinate differences between position coordinates of the output digital signals and position coordinates of the input digital signals adjacent to the position coordinates. An FIR coefficient memory (13a to 13c) stores FIR coefficients of an FIR-LPF and outputs FIR coefficients corresponding to position coordinate differences between a fixed number of the output digital signals adjacent to the position coordinates of the output digital signals and the output digital signals. A control unit (11) supplies a group of the FIR coefficients and a group of the input digital signals corresponding to the respective position coordinate differences to the parallel FIR calculator (4) in predetermined order when the position coordinate differences corresponding to two or more different output digital signals are concurrently computed. The parallel FIR calculator (4) performs an FIR-LPF interpolating calculation by using those to obtain the output digital signals.

An apparatus for processing an audio signal includes a configurable first audio signal processor for processing the audio signal in accordance with different configuration settings to obtain a processed audio signal, wherein the apparatus is adapted so that different configuration settings result in different sampling rates of the processed audio signal. The apparatus furthermore includes n analysis filter bank having a first number of analysis filter bank channels, a synthesis filter bank having a second number of synthesis filter bank channels, a second audio processor being adapted to receive and process an audio signal having a predetermined sampling rate, and a controller for controlling the first number of analysis filter bank channels or the second number of synthesis filter bank channels in accordance with a configuration setting.

An apparatus for processing an audio signal includes a configurable first audio signal processor for processing the audio signal in accordance with different configuration settings to obtain a processed audio signal, wherein the apparatus is adapted so that different configuration settings result in different sampling rates of the processed audio signal. The apparatus furthermore includes n analysis filter bank having a first number of analysis filter bank channels, a synthesis filter bank having a second number of synthesis filter bank channels, a second audio processor being adapted to receive and process an audio signal having a predetermined sampling rate, and a controller for controlling the first number of analysis filter bank channels or the second number of synthesis filter bank channels in accordance with a configuration setting.

There is a need for high-order frequency measurement without greatly increasing consumption currents and chip die sizes. A semiconductor device includes: an electric power measuring portion that performs electric power measurement; a high-order frequency measuring portion that performs high-order frequency measurement; and a clock controller that supplies an electric power measuring portion with a first clock signal at a first sampling frequency and supplies a high-order frequency measuring portion with a second clock signal at a second sampling frequency. The second sampling frequency is higher than the first sampling frequency.

A detector device for calibrating a digital filter to replicate a transfer function of a signal processing apparatus, comprising: a first input to receive a first signal; a second input configured to receive a response signal of the signal processing apparatus to the first signal; a controllable FIR filter; a comparison-block to compare the phase and amplitude after a correction has been applied by the controllable FIR filter; a feedback loop; and an interpolation-block; wherein the at least one detector is configured to determine, at least, the feedback control signal at a first frequency and at a second frequency, and wherein the interpolation-block is configured to interpolate to determine calibration information for programming of the transfer function of said digital filter.

An upper limit of a frequency range of audio indicated by input audio data is detected. A representative point extraction unit downsamples the input audio data to a sampling rate set to be less than or equal to twice the detected upper limit to obtain representative-point audio data. An interpolation processing unit upsamples the representative-point audio data by using a fractal interpolation function (FIF) that uses a mapping function calculated by a mapping function calculation unit, while using the input audio data, if necessary, to generate high-frequency interpolated audio data.

An integrated circuit device can include at least one input; at least one output configured to provide a multi-bit output value; at least one input; at least one output configured to provide a multi-bit output value; a plurality of configurable digital filter circuits; and switch circuits coupled to the at least one input and to the at least one output, the switch circuits configurable to connect same digital filter circuits as a single processing path or separate processing paths.

Data samples are filtered by using a digital filter where the length of an impulse response of the digital filter is finite, an impulse response of the digital filter is symmetric and the operation of the digital filter is multi-rate. The method uses a polyphase decomposition to break down the input data stream into N parallel substreams and the multi-rate digital filter is separated by a polyphase decomposition into multiple lower-rate sub-filters where each of the sub-filters is separated into a set of simpler sub-sub-filters which operate upon the same set of input samples and which have impulse responses which are jointly centro-symmetric, a set of pre-filtering arithmetic structures, and a set of post-filtering arithmetic structures and performing each such pair of sub-sub-filtering operations using a single shared filter structure, a set of pre-filtering combining adders, and a set of post-filtering separating adders.

There is a need for high-order frequency measurement without greatly increasing consumption currents and chip die sizes. A semiconductor device includes: an electric power measuring portion that performs electric power measurement; a high-order frequency measuring portion that performs high-order frequency measurement; and a clock controller that supplies an electric power measuring portion with a first clock signal at a first sampling frequency and supplies a high-order frequency measuring portion with a second clock signal at a second sampling frequency. The second sampling frequency is higher than the first sampling frequency.

A method for resampling an audio-frequency signal with an output sampling frequency, for a current signal frame. The method is used when the preceding frame is sampled at a first sampling frequency which is different from a second sampling frequency of the current frame. The method includes: determining a first and second segments of the signal by adding samples at zero at the end of stored samples of the preceding frame and at the start of samples of the current frame, respectively; obtaining the first resampled segment and the second resampled segment by applying at least one resampling filter respectively to the first segment resampling the first frequency at the output frequency, and to the second segment resampling the second frequency at the output frequency; and combining the overlapping portion of the first and second resampled segments to obtain at least one portion of the resampled current frame.