A regenerative frequency divider comprising an in-phase mixer circuit and a phase-shifted mixer circuit. At least one switching device of the in-phase mixer circuit is of a smaller scale than a corresponding switching device of the transconductance component of the in-phase mixer circuit. In some examples, at least one switching device within an input switching stage of the regenerative frequency divider forming part of the phase-shifted mixer circuit is of a smaller scale than a respective corresponding switching device within the input switching stage forming part of the in-phase mixer circuit. In some further examples, all switching devices within the phase-shifted mixer circuit are of a small scale than respective corresponding switching devices within the in-phase mixer circuit.

A regenerative frequency divider comprising an in-phase mixer circuit and a phase-shifted mixer circuit. At least one switching device of the in-phase mixer circuit is of a smaller scale than a corresponding switching device of the transconductance component of the in-phase mixer circuit. In some examples, at least one switching device within an input switching stage of the regenerative frequency divider forming part of the phase-shifted mixer circuit is of a smaller scale than a respective corresponding switching device within the input switching stage forming part of the in-phase mixer circuit. In some further examples, all switching devices within the phase-shifted mixer circuit are of a small scale than respective corresponding switching devices within the in-phase mixer circuit.

A clock generation circuit includes a temperature compensation circuit and an oscillator. The temperature compensation circuit is configured to generate a temperature-compensated frequency selection code that varies depending on an operation temperature based on a difference between the operation temperature and a reference temperature and based on a temperature-independent frequency selection code that is fixed regardless of the operation temperature. The oscillator is configured to generate a clock signal that has an operation frequency that is based on the temperature-compensated frequency selection code, such that the operation frequency is uniform regardless of the operation temperature. Effects of the operation temperature may be reduced by generating the temperature-compensated frequency selection code that reflects the temperature characteristic of the oscillator using the output value of the temperature sensor and by controlling the oscillator using the temperature-compensated frequency selection code.

Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has a step-down converter coupled to an oscillator between a first voltage supply and a second voltage supply. The second stage is coupled to the first stage, and the second stage has a current bias generator coupled to a diode-connected transistor between the first voltage supply and the second voltage supply. The second stage provides an intermediate voltage to the first stage.

A successive-approximation register (SAR) analog-to-digital converter (ADC) circuit includes a comparator circuit and a plurality of latch circuits. The comparator circuit is configured to compare an analog signal with a plurality of reference levels. The latch circuits, coupled to the comparator circuit and connected in series, are triggered sequentially in response to a plurality of trigger signals, respectively, to store a comparator output of the comparator circuit and accordingly generate a digital signal. A first latch circuit and a second latch circuit of the latch circuits are triggered in response to a first trigger signal and a second trigger signal of the trigger signals, respectively. The first latch circuit is configured to generate the second trigger signal according to the comparator output stored in the first latch circuit.

The present disclosure relates to an oscillator including a charge and discharge circuit which generates a first oscillation signal according to a clock signal using a first constant current and a second oscillation signal according to an inverted clock signal using a second constant current, an integrating circuit which generates a first comparison voltage reflecting an amount of change in the first oscillation signal based on a comparison reference voltage and a second comparison voltage reflecting an amount of change in the second oscillation signal based on the comparison reference voltage, and a comparison circuit which generates the clock signal and the inverted clock signal according to a result of comparison between the first oscillation signal and the first comparison voltage and a result of comparison between the second oscillation signal and the second comparison voltage.

A type of rotating disk magnetic field probe (1) comprising: a non-magnetic rotating disk (2), 4N first soft ferromagnetic sectors (3), M second soft ferromagnetic sectors (4), a reference signal generator, an X-axis magnetoresistive sensor (7, 8), a Y-axis magnetoresistive sensor (5,6), and a Z-axis magnetoresistive sensor (9). Both the first soft ferromagnetic sectors (3) and the second soft ferromagnetic sector (4) are located on the non-magnetic rotating disk (2). In operation, the non-magnetic rotating disk (2) rotates about a Z-axis at a frequency f. An external magnetic field is modulated by the first soft ferromagnetic sector (3) into an X-axis magnetic field sensed component and a Y-axis magnetic field sensed component having a frequency of 4N×f, and is modulated by the second soft ferromagnetic field sectors into a Z-axis magnetic field sensed component having a frequency of M×f. The X-axis sensed magnetic field component, the Y-axis sensed magnetic field component, and the Z-axis sensed magnetic field component respectively are converted into output signals by means of the X-axis magnetoresistive sensor (7, 8) the Y-axis magnetoresistive sensor (5, 6) and the Z-axis magnetoresistive sensor (9). The reference signal generator respectively outputs a first reference signal having a frequency of 4N×f and a second reference signal having a frequency of M×f. The first reference signal, the second reference signal, and the measurement signals are demodulated by an external processing circuit to output magnetic field values Hx, Hy and Hz.

An oscillator circuit includes an initial level setting circuit configured to operate in an on-state during an initial operation of the oscillator circuit to supply a first level voltage to a first node and a second level voltage to a second node, a switching circuit configured to connect a power supply voltage terminal and a ground terminal to the first or second node in response to first and second clock signals having different phases after the initial operation, a signal generation circuit connected between the first and second nodes and configured to perform charging and discharging operations based on a potential difference between the first and second nodes, and generate first and second voltages determined by the charging and discharging operations, and an inverter circuit configured to generate the first clock signal based on the first voltage, and generate the second clock signal based on the second voltage.

Various embodiments relate to a free running oscillator, that includes a switch capacitor based frequency-to-voltage converter (F2V), a comparator, and a voltage controlled oscillator (VCO), which may be collectively configured to reduce amplifier offset and flicker noise while increasing effective gain of the amplifier of the comparator. The F2V may produce a feedback voltage Vfb corresponding to frequencies of output of the VCO. The comparator may be configured to sample a reference voltage Vref using a sampling capacitor, compare Vref to Vfb, and generate an output based on any difference between Vref and Vfb, where the output may be integrated using an integrating capacitor of the comparator. The comparator may compensate for parasitic capacitance at the output of the amplifier by using an amplifier having two outputs, with the sampling capacitor and integrating capacitor being coupled to respectively different outputs of the amplifier.

Various embodiments relate to a free running oscillator, that includes a switch capacitor based frequency-to-voltage converter (F2V), a comparator, and a voltage controlled oscillator (VCO), which may be collectively configured to reduce amplifier offset and flicker noise while increasing effective gain of the amplifier of the comparator. The F2V may produce a feedback voltage Vfb corresponding to frequencies of output of the VCO. The comparator may be configured to sample a reference voltage Vref using a sampling capacitor, compare Vref to Vfb, and generate an output based on any difference between Vref and Vfb, where the output may be integrated using an integrating capacitor of the comparator. The comparator may compensate for parasitic capacitance at the output of the amplifier by using an amplifier having two outputs, with the sampling capacitor and integrating capacitor being coupled to respectively different outputs of the amplifier.