A system may include a Class-D stage comprising a first high-side switch coupled between a supply voltage and a first output terminal of the Class-D stage, a second high-side switch coupled between the supply voltage and a second output terminal of the Class-D stage, a first low-side switch coupled between a ground voltage and the first output terminal, and a second low-side switch coupled between the ground voltage and the second output terminal. The system may also include current sensing circuitry comprising a sense resistor, such that an output current through a load coupled between the first output terminal and the second output terminal causes a first sense voltage proportional to the output current across the sense resistor. The system may additionally include a modulator for generating a differential pulse-width modulation driving signal to the first high-side switch, the second high-side switch, the first low-side switch, and the second low-side switch and pilot tone injection circuitry configured to inject a periodic pilot tone into the differential pulse-width modulation driving signal at a pilot tone frequency.

A successive-approximation register (SAR) analog-to-digital converter (ADC) circuit includes a comparator circuit and a plurality of latch circuits. The comparator circuit is configured to compare an analog signal with a plurality of reference levels. The latch circuits, coupled to the comparator circuit and connected in series, are triggered sequentially in response to a plurality of trigger signals, respectively, to store a comparator output of the comparator circuit and accordingly generate a digital signal. A first latch circuit and a second latch circuit of the latch circuits are triggered in response to a first trigger signal and a second trigger signal of the trigger signals, respectively. The first latch circuit is configured to generate the second trigger signal according to the comparator output stored in the first latch circuit.

A differential amplifier circuit generates a first current and a second current having a current difference obtained by amplifying a voltage difference between an input voltage and a reference voltage. An output stage supplies current proportional to the first current to an output node. A current conversion circuit discharges current proportional to the second current from the output node. After connecting the output node to a ground node in response to a reset signal, a latch circuit disconnects the output node from the ground node after reset cancellation. Thereafter, when voltage at the output node rises from the ground voltage in a case where a level relationship between the input voltage and the reference voltage is reversed from a reset cancellation time point, the latch circuit fixes the voltage at the output node to a power supply voltage by a positive feedback latch operation.

An oscillator circuit includes an integrator, a comparator, an edge triggered flip-flop, and first and second capacitors. The edge triggered flip-flop has an input terminal coupled to an output terminal of the comparator and is configured to output first and second signals which are mutually exclusive, and to flip the signals when detecting a rising or falling edge output by the comparator such that: when the first signal is at a designated level, the first capacitor is charged and the second capacitor is discharged, and a terminal of the first capacitor is coupled to an input terminal of the integrator; and when the second signal is at a designated level, the second capacitor is charged and the first capacitor is discharged and a terminal of the second capacitor is coupled to the input terminal of the integrator.

An oscillator circuit includes an integrator, a comparator, an edge triggered flip-flop, and first and second capacitors. The edge triggered flip-flop has an input terminal coupled to an output terminal of the comparator and is configured to output first and second signals which are mutually exclusive, and to flip the signals when detecting a rising or falling edge output by the comparator such that: when the first signal is at a designated level, the first capacitor is charged and the second capacitor is discharged, and a terminal of the first capacitor is coupled to an input terminal of the integrator; and when the second signal is at a designated level, the second capacitor is charged and the first capacitor is discharged and a terminal of the second capacitor is coupled to the input terminal of the integrator.

The present disclosure relates to a frequency modulation device, a switching power supply and a frequency modulation method thereof. The device includes: a waveform generation unit (10) configured to generate a periodic signal required for performing frequency modulation on a clock signal of a switching power supply to be controlled; a frequency modulation unit (20) configured to perform voltage-current conversion and arithmetic processing based on the periodic signal to obtain a frequency modulation current required for performing the frequency modulation on the clock signal of the switching power supply to be controlled; and an RC oscillation unit (30) configured to perform RC oscillation processing based on the frequency modulation current to obtain a frequency oscillation signal as the clock signal of the switching power supply to be controlled.

An integrated circuit is built with enhancement mode Gallium Nitride (GaN) components. The integrated circuit comprises a comparator circuit which compares an input voltage with a reference voltage to provide a controllable constant current source, the comparator having a drive transistor having a positive threshold voltage, the drive transistor being switched on and off based on a comparison result of the comparator. The circuit may drive ring oscillators and may provide pulse width modulation with variable duty cycle at constant frequency.

An integrated circuit is built with enhancement mode Gallium Nitride (GaN) components. The integrated circuit comprises a comparator circuit which compares an input voltage with a reference voltage to provide a controllable constant current source, the comparator having a drive transistor having a positive threshold voltage, the drive transistor being switched on and off based on a comparison result of the comparator. The circuit may drive ring oscillators and may provide pulse width modulation with variable duty cycle at constant frequency.

The present invention provides an oscillator circuit and a semiconductor integrated circuit, which can suppress the upper limit of the frequency of a clock signal due to an error of the constant current circuit. The oscillator circuit of the present invention includes a constant current circuit, an oscillator, and a current limiting circuit. The constant current circuit generates a first output current according to a supply voltage. The current limiting circuit receives the first output current and generates a second output current, and establishes an upper limit for the second output current when the supply voltage drops below a lower limit of a guaranteed operational range of the constant current circuit. The oscillator generates a clock signal according to the second output current. By establishing the upper limit for the second output current, the upper limit of the frequency of the clock signal can be suppressed.

The present invention provides an oscillator circuit and a semiconductor integrated circuit, which can suppress the upper limit of the frequency of a clock signal due to an error of the constant current circuit. The oscillator circuit of the present invention includes a constant current circuit, an oscillator, and a current limiting circuit. The constant current circuit generates a first output current according to a supply voltage. The current limiting circuit receives the first output current and generates a second output current, and establishes an upper limit for the second output current when the supply voltage drops below a lower limit of a guaranteed operational range of the constant current circuit. The oscillator generates a clock signal according to the second output current. By establishing the upper limit for the second output current, the upper limit of the frequency of the clock signal can be suppressed.