A voltage-controlled delay line including a clipper configured to produce a clipped input voltage from an input voltage, an oscillator configured to produce a strobe pulse train that is initiated by the clipped input voltage, and a divider module configured to divide the strobe pulse train and produce an output voltage from the divided strobe pulse train.

A phase locked loop system has a voltage-controlled variable-load ring oscillator (VLCO) that operates in a frequency band determined by a selected load on each stage of the ring oscillator. Each stage of the VLCO has multiple load selection transistors, each coupled to a load capacitor. Apparatus is provided for driving the load selection transistors according to a load configuration; and apparatus is provided for determining an operating load configuration such that a period of a divided reference signal approximately matches a period of a divided VLCO signal with the VLCO control voltage input clamped to a reference voltage. Once the load configuration is set, the loop is allowed to lock. In a particular embodiment, devices are provided for slowly tweaking the VLCO load to help keep the VLCO operating near an optimum control voltage despite drift of circuit parameters with temperature or time.

A signal may be arbitrarily delayed in discrete steps by an arbitrary delay buffer having an analog delay and a digital delay. An analog delay may have a number of selectable delay stages (e.g. ring oscillator with VCDL stages). A digital delay may have rising and falling edge detectors, resettable ring oscillators that oscillate in response to rising or falling edges and counters to count oscillations and generate rising and falling edge delay signals when oscillation counts reach rising and falling edge delay counts. A resettable ring oscillator may have a resettable stage (e.g. VCDL) that may be enabled and disabled. Selection of one or both digital and analog delays and respective delay times may be based on one or more characteristics. For example, an analog delay may delay an input signal or a delayed input signal received from the digital delay based on input signal frequency or total delay.

Disclosed embodiments select a proper hum frequency reference by utilizing one or more functional logic circuits within a cluster. he slowest logic circuit is determined, and an instance of that logic circuit is used in timing circuitry for the cluster. Multiple logic circuits with similar characteristics are incorporated into the timing circuit. Each cluster is interconnected to a second level timing circuit. Each cluster inputs timing information into the second level timing circuit. The second level timing circuit then determines when the next cycle, or tic, of the self-generated clock starts, and the process repeats, providing a self-generated clock signal.

A frequency stable oscillator with compensation circuit, the device includes a ring oscillator circuit having S number of stages, a current generator circuit configured to generate a first current, a replica circuit having an inverter with output connected to input, configured to generate a first voltage upon dumping a second current onto the replica circuit, a first operational transconductance amplifier (OTA) with an input as the first voltage, configured to generate a third current and a current mirror circuit configured to generate a fourth current by adding the first current and the third current in a particular ratio M:N, wherein the inverter of the replica circuit is equivalent to a single stage of the ring oscillator circuit and wherein the fourth current is the total current for the ring oscillator circuit and is as close as possible to S times the second current.

In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.

Example embodiments of systems, methods, and computer-accessible mediums for identity verification and transaction authentication are provided. An exemplary system can comprise an application, a user device, and a server. The application can prompt a removal of a card chip, prompt an insertion of the card chip into the user device, determine an orientation of the card chip after the insertion of the card chip into the user device, and transmit, to the card chip, a first message. The card chip can encrypt the first message via one or more authentication protocols to generate an encrypted first message, transmit, to the server, the encrypted first message. The server can decrypt the encrypted first message, verify the decrypted first message, and transmit a second message to the application, wherein the application is configured to display a verification notification in response to the second message.

An oscillator circuit having a programmable output frequency may include a first delay section having a negative gain and a variable delay that is set by a control signal provided to the first delay section. A second delay section having a negative gain and a fixed delay may be connected in series with the first delay section. The oscillator circuit may include an output comprising the output of the second delay section having a frequency that is dependent on the delay of the first delay section and the delay of second delay section.

An oscillator circuit having a programmable output frequency may include a first delay section having a negative gain and a variable delay that is set by a control signal provided to the first delay section. A second delay section having a negative gain and a fixed delay may be connected in series with the first delay section. The oscillator circuit may include an output comprising the output of the second delay section having a frequency that is dependent on the delay of the first delay section and the delay of second delay section.

A circuit may include a ring oscillator circuit and monitoring circuitry. The ring oscillator circuit has a group of inverters in a loop, whereby the group of inverters includes first, second, and third output nodes. The monitoring circuitry may monitor for error events in a signal that has passed through the inverters from any one of the first, second, or third output nodes, and may generate first and second monitoring circuitry outputs. The circuit may further include an error correction circuit that produces an error correction output based on the first and second monitoring circuitry outputs. Accordingly, the monitoring circuitry may generate first and second updated monitoring circuitry outputs based on the error correction output. The first and second updated monitoring circuitry outputs may be logically combined using a logic circuit to reset the signal that has passed through the loop.