Disclosed examples include self-biased DLL circuits to generate a bias current signal proportional to a repetition frequency of a first signal representing continuous switching or discontinued switching operation of the DC-DC converter. The DLL circuit includes a monostable multivibrator to provide a pulse output signal in response to an edge of the first signal with a pulse duration set by a control current signal, a phase detector to provide output signals according to a phase difference between an edge of the pulse output signal and the first signal, and an output circuit to provide an output signal according to the phase detector output signals and according to an offset signal, to provide the bias current signal according to the output signal, and to provide the control current signal according to the output signal.

A transimpedance amplifier may include a voltage-controlled operational amplifier having a non-inverting input connected to ground, an inverting input receiving a current signal to be amplified, an output coupled to the inverting input via a coupling resistor, and a power-down input (PWDN input) activated upon receipt of at least one power-down signal (PWDN) such that at least one internal current source is thereupon deactivated.

A transimpedance amplifier may include a voltage-controlled operational amplifier having a non-inverting input connected to ground, an inverting input receiving a current signal to be amplified, an output coupled to the inverting input via a coupling resistor, and a power-down input (PWDN input) activated upon receipt of at least one power-down signal (PWDN) such that at least one internal current source is thereupon deactivated.

A short pulse generating circuit including a pulse generating circuit, an actuation control circuit and a delay control circuit is provided. The pulse generating circuit is electrically coupled to a switch, which is coupled to a power. When the power is turned on, the power causes the pulse generating circuit to generate a long pulse. The actuation control circuit is electrically coupled to the power and the pulse generating circuit. When the power is turned on, the actuation control circuit controls a voltage level of each output of the pulse generating circuit to a fixed value. The delay control circuit is electrically coupled to the pulse generating circuit. When the switch is turned on, the power controls the delay control circuit to change the voltage level of each output of the pulse generating circuit to generate a short pulse output.

Voltage surge is prevented when the output from a driver of a driving circuit performs a hard shutdown. In this manner, the elements in the driving circuit are prevented from being damaged by the voltage surge. A driving circuit includes a level shift circuit configured to convert an input signal from a preceding-stage circuit into an output signal having a higher voltage than the input signal, and a controller configured to determine whether a switch element is to perform a soft shutdown based on a state signal indicating a state of the preceding-stage circuit. Here, the driving circuit is configured to drive the switch element.

Voltage surge is prevented when the output from a driver of a driving circuit performs a hard shutdown. In this manner, the elements in the driving circuit are prevented from being damaged by the voltage surge. A driving circuit includes a level shift circuit configured to convert an input signal from a preceding-stage circuit into an output signal having a higher voltage than the input signal, and a controller configured to determine whether a switch element is to perform a soft shutdown based on a state signal indicating a state of the preceding-stage circuit. Here, the driving circuit is configured to drive the switch element.

A surgical instrument is disclosed comprising a control system and a strain gage circuit. The operation of the control system is modifiable by an input from the strain gage circuit.

An interactive control unit is disclosed. The interactive control unit includes an interactive touchscreen display, an interface configured to couple the control unit to a surgical hub, a processor, and a memory coupled to the processor. The memory stores instructions executable by the processor to receive input commands from the interactive touchscreen display located inside a sterile field and transmit the input commands to the surgical hub to control devices coupled to the surgical hub located outside the sterile field.

A short pulse generating circuit including a pulse generating circuit, an actuation control circuit and a delay control circuit is provided. The pulse generating circuit is electrically coupled to a switch, which is coupled to a power. When the power is turned on, the power causes the pulse generating circuit to generate a long pulse. The actuation control circuit is electrically coupled to the power and the pulse generating circuit. When the power is turned on, the actuation control circuit controls a voltage level of each output of the pulse generating circuit to a fixed value. The delay control circuit is electrically coupled to the pulse generating circuit. When the switch is turned on, the power controls the delay control circuit to change the voltage level of each output of the pulse generating circuit to generate a short pulse output.

The techniques described herein relate to duty cycle error calibration. An example apparatus includes a multi-modulus divider (MMD) circuit configured to receive a first digital code corresponding to a first time delay and included in a first plurality of digital codes associated with a first range of time delays, divide a clock signal by a divisor to generate a divided clock signal, and delay the divided clock signal by the first time delay to generate a delayed clock signal. The apparatus may further include a digitally controlled delay line (DCDL) circuit configured to receive a second digital code corresponding to a second time delay and included in a second plurality of digital codes associated with a second range of time delays, and delay the delayed clock signal by the second time delay to generate a feedback clock signal to reduce a difference between the feedback and a reference clock signal.