An electrical control system which controls an electrical device from two or more locations with independent control function, the system including a wall adapter having a first integrated circuit board, a first enclosure, and a second enclosure. The first enclosure includes a first push button, a first synchronizing push button, and a second IC board electrically connected to the wall adapter; and the second enclosure includes a second push button, a second synchronizing push button, and a third IC board. Each of the wall switch, the first synchronizing push button, and the second synchronizing push button is a system power control button and part of a synchronizing circuit that synchronizes the electrical control system to default system power controls upon being pressed by a user. Each of the first and second push buttons is a local button that controls a respective controlled receptable of a respective enclosure.

An electrical control system which controls an electrical device from two or more locations with independent control function, the system including a wall adapter having a first integrated circuit board, a first enclosure, and a second enclosure. The first enclosure includes a first push button, a first synchronizing push button, and a second IC board electrically connected to the wall adapter; and the second enclosure includes a second push button, a second synchronizing push button, and a third IC board. Each of the wall switch, the first synchronizing push button, and the second synchronizing push button is a system power control button and part of a synchronizing circuit that synchronizes the electrical control system to default system power controls upon being pressed by a user. Each of the first and second push buttons is a local button that controls a respective controlled receptable of a respective enclosure.

Disclosed herein is an apparatus that includes a data serializer including a plurality of first buffer circuits configured to receive a plurality of data, respectively, and a second buffer circuit configured to serialize the plurality of data provided from the plurality of first buffer circuits. At least one of the plurality of first buffer circuits and the second buffer circuit includes: a first circuit configured to drive a first signal node to one of first and second logic levels based on an input signal, the first circuit including a first adjustment circuit configured to adjust a driving capability of the first circuit when the first circuit drives the first signal node to the first logic level; and a second circuit configured to drive the first signal node to other of the first and second logic levels.

Disclosed herein is an apparatus that includes a data serializer including a plurality of first buffer circuits configured to receive a plurality of data, respectively, and a second buffer circuit configured to serialize the plurality of data provided from the plurality of first buffer circuits. At least one of the plurality of first buffer circuits and the second buffer circuit includes: a first circuit configured to drive a first signal node to one of first and second logic levels based on an input signal, the first circuit including a first adjustment circuit configured to adjust a driving capability of the first circuit when the first circuit drives the first signal node to the first logic level; and a second circuit configured to drive the first signal node to other of the first and second logic levels.

The redundancy control device includes three controllers that output status signals, a majority voting circuit to which a first voltage or a second voltage is supplied as an output signal through an output line of each controller, a switch provided in each output line, a voltage supply unit provided for each output line to supply the second voltage to the output line when the first voltage is lost, a latch circuit provided for each output line to latch the second voltage when the second voltage is supplied thereto and continue to output the second voltage, a comparison circuit provided for each controller to output a comparison signal based on a comparison of the status signals, and a switch control unit provided for each switch to outputs a switch signal to the switch in response to the comparison signal from the comparison circuit.

The redundancy control device includes three controllers that output status signals, a majority voting circuit to which a first voltage or a second voltage is supplied as an output signal through an output line of each controller, a switch provided in each output line, a voltage supply unit provided for each output line to supply the second voltage to the output line when the first voltage is lost, a latch circuit provided for each output line to latch the second voltage when the second voltage is supplied thereto and continue to output the second voltage, a comparison circuit provided for each controller to output a comparison signal based on a comparison of the status signals, and a switch control unit provided for each switch to outputs a switch signal to the switch in response to the comparison signal from the comparison circuit.

A master-slave flip-flop includes a first latch, a second latch and a tristate driver. The first latch has a combined input/output that is coupled with a common node, a pm output, and an nm output. The tristate driver has pm and nm inputs coupled with the pm and nm outputs of the first latch, and a tristate output coupled with the common node. A pm input signal prevents the tristate driver from pulling the common node high, and an nm input signal prevents the tristate driver from pulling the common node low. The second latch is directly coupled with the common node. The first latch generates an nm signal and a pm signal in response to a signal on the first latch clk input and a state of the common node, wherein the pm signal and the nm signal have opposite polarities when the signal on the first latch clk input has a first value, and equal polarities when the signal on the first latch clk input has a second value.

A fixed time-delay circuit of a high-speed interface is disclosed. The fixed time-delay circuit comprises: a counter circuit for generating a shift selection signal of any bit; a data selector circuit for receiving first parallel data signals and rearranging the first parallel data signals according to the shift selection signal and a first low-speed clock to obtain second parallel data signals; a clock selector circuit for selecting, according to the shift selection signal, one clock from multiple input clocks having different phases, for outputting, to form a second low-speed clock; and a synchronization circuit for synchronizing the second parallel data signals according to the second low-speed clock. According to the circuit, initialization alignment among multichannel data of the high-speed interface can be achieved.

A fixed time-delay circuit of a high-speed interface is disclosed. The fixed time-delay circuit comprises: a counter circuit for generating a shift selection signal of any bit; a data selector circuit for receiving first parallel data signals and rearranging the first parallel data signals according to the shift selection signal and a first low-speed clock to obtain second parallel data signals; a clock selector circuit for selecting, according to the shift selection signal, one clock from multiple input clocks having different phases, for outputting, to form a second low-speed clock; and a synchronization circuit for synchronizing the second parallel data signals according to the second low-speed clock. According to the circuit, initialization alignment among multichannel data of the high-speed interface can be achieved.

A latch array including a row of master latches coupled to columns of slave latches. Each master latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch an input data, and each slave latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch the data from the master latch, and an inverter including an input coupled to the AOI gate and an output to produce an output data based on the input data. Alternatively, each master latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch an input data, and each slave latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch the data from the master latch, and an inverter including an input coupled to the OAI gate and an output to produce an output data.