The present invention provides a frequency-halving latch circuit for deterministic field bus network data forwarding and application thereof. The frequency-halving latch circuit includes a data buffer equipped with two buffer units; a frequency-halving enable latch signal generation module for generating a first frequency-halving latch signal and a second frequency-halving latch signal with opposite levels, and selecting data buffer units of the data buffer based on the first frequency-halving latch signal, the second frequency-halving latch signal and a receiving enable signal; and a shift register including a first trigger and a second trigger which are initialized to opposite output states, the first trigger and the second trigger is connected to realize a shift operation, and data stored in the data buffer units is finally selected and read based on a low order in the shift register composed of the two triggers and a read enable signal. The frequency-halving latch circuit can be applied to a scenario of deterministic field bus network data forwarding as a same-frequency out-of-phase data cross-clock domain circuit, with high resource utilization rate and stability.

The present invention provides a frequency-halving latch circuit for deterministic field bus network data forwarding and application thereof. The frequency-halving latch circuit includes a data buffer equipped with two buffer units; a frequency-halving enable latch signal generation module for generating a first frequency-halving latch signal and a second frequency-halving latch signal with opposite levels, and selecting data buffer units of the data buffer based on the first frequency-halving latch signal, the second frequency-halving latch signal and a receiving enable signal; and a shift register including a first trigger and a second trigger which are initialized to opposite output states, the first trigger and the second trigger is connected to realize a shift operation, and data stored in the data buffer units is finally selected and read based on a low order in the shift register composed of the two triggers and a read enable signal. The frequency-halving latch circuit can be applied to a scenario of deterministic field bus network data forwarding as a same-frequency out-of-phase data cross-clock domain circuit, with high resource utilization rate and stability.

A random bit generator includes a voltage source, a bit data cell, and a sensing control circuit. The voltage source provides a scan voltage during enroll operations. The data cell includes a first transistor and a second transistor. The first transistor has a first terminal coupled to a first bit line, a second terminal coupled to the voltage source, and a control terminal. The second transistor has a first terminal coupled to a second bit line, a second terminal coupled to the voltage source, and a control terminal. The sensing control circuit is coupled to the first bit line and the second bit line, and outputs a random bit data according to currents generated through the first transistor and the second transistor during an enroll operation of the bit data cell.

A random bit generator includes a voltage source, a bit data cell, and a sensing control circuit. The voltage source provides a scan voltage during enroll operations. The data cell includes a first transistor and a second transistor. The first transistor has a first terminal coupled to a first bit line, a second terminal coupled to the voltage source, and a control terminal. The second transistor has a first terminal coupled to a second bit line, a second terminal coupled to the voltage source, and a control terminal. The sensing control circuit is coupled to the first bit line and the second bit line, and outputs a random bit data according to currents generated through the first transistor and the second transistor during an enroll operation of the bit data cell.

A serial bus re-driver circuit includes an edge detector circuit and a booster circuit. The edge detector circuit is configured to detect a transition of serial bus signal. The booster circuit is coupled to the edge detector circuit, and is configured to switch current to the serial bus signal. The booster circuit includes a leading edge boost pulse generation circuit and a trailing edge boost pulse generation circuit. The leading edge boost pulse generation circuit is configured to switch a first current pulse to the serial bus signal at the transition of the serial bus signal. The trailing edge boost pulse generation circuit is configured to switch a second current pulse to the serial bus signal. The second current pulse is shorter than the first current pulse.

A serial bus re-driver circuit includes an edge detector circuit and a booster circuit. The edge detector circuit is configured to detect a transition of serial bus signal. The booster circuit is coupled to the edge detector circuit, and is configured to switch current to the serial bus signal. The booster circuit includes a leading edge boost pulse generation circuit and a trailing edge boost pulse generation circuit. The leading edge boost pulse generation circuit is configured to switch a first current pulse to the serial bus signal at the transition of the serial bus signal. The trailing edge boost pulse generation circuit is configured to switch a second current pulse to the serial bus signal. The second current pulse is shorter than the first current pulse.

The present disclosure includes an integrated circuit comprising a first pair of complementary transistors configured in series, a second pair of complementary transistors configured in series, and at least one charge extraction transistor having a gate coupled to a first potential, a source coupled to a second potential, and a drain coupled to a data storage node of one of the first or second pairs of complementary transistors. The first potential and second potential bias the at least one charge extraction transistor in a nonconductive state. The drain of the at least one charge extraction transistor is formed in a doped material shared with a drain of a transistor of the first or second pairs of complementary transistors.

The present disclosure includes an integrated circuit comprising a first pair of complementary transistors configured in series, a second pair of complementary transistors configured in series, and at least one charge extraction transistor having a gate coupled to a first potential, a source coupled to a second potential, and a drain coupled to a data storage node of one of the first or second pairs of complementary transistors. The first potential and second potential bias the at least one charge extraction transistor in a nonconductive state. The drain of the at least one charge extraction transistor is formed in a doped material shared with a drain of a transistor of the first or second pairs of complementary transistors.

A radio frequency (RF) generator includes a pulse generator circuit configured to receive input signals indicative of a pulse pattern comprising pulse segments, the input signals defining power levels and durations for the pulse segments. The pulse generator circuit generates a pulse modulation control signal for each pulse segment responsive to the input signals. The pulse modulation control signal is coupled to adjust an amplitude and to modulate an RF source signal to generate the pulse RF signal having an envelope defined by the pulse segments of the pulse pattern.

A radio frequency (RF) generator includes a pulse generator circuit configured to receive input signals indicative of a pulse pattern comprising pulse segments, the input signals defining power levels and durations for the pulse segments. The pulse generator circuit generates a pulse modulation control signal for each pulse segment responsive to the input signals. The pulse modulation control signal is coupled to adjust an amplitude and to modulate an RF source signal to generate the pulse RF signal having an envelope defined by the pulse segments of the pulse pattern.