The disclosure discloses a lookup table-based circuit aging detection sensor, including a control circuit, two voltage controlled oscillators (VCOs), two shaping circuits, a phase comparator, a 3-digit voter, a beat-frequency oscillator, an 8-digit counter, a latch, a lookup table array and a digital-analogue converter. The control circuit respectively connects with the phase comparator, the 3-digit voter, the 8-digit counter, the first and the second VCOs. The first and second VCOs connect with the first and second shaping circuits respectively. The first and second shaping circuits connect with the phase comparator. The phase comparator connects with the 3-digit voter. The 3-digit voter connects with the beat-frequency oscillator. The beat-frequency oscillator respectively connects with the 8-digit counter and the latch. The 8-digit counter connects with the latch. The latch connects with the lookup table array. The lookup table array connects with the digital-analogue converter.

The disclosure relates to a skew control circuit for controlling the skew between at least three clock signals, the clock signals being forwarded to different clock domains associated with the respective clock signals. The skew control circuit comprises multiple programmable delay elements arranged within a signal flow before the respective clock domain, a skew detector arrangement operable for detecting skews between at least two pairs of the clock signals, and a control circuit operable for adjusting delays caused by the programmable delay elements. The control circuit is operable for carrying out a de-skewing operation. The de-skewing operation comprises determining an order of occurrence of edges of the signals, selecting one of the programmable delay elements based on the determined order, and adjusting the delay caused by the selected programmable delay element.

The disclosure relates to a skew control circuit for controlling the skew between at least three clock signals, the clock signals being forwarded to different clock domains associated with the respective clock signals. The skew control circuit comprises multiple programmable delay elements arranged within a signal flow before the respective clock domain, a skew detector arrangement operable for detecting skews between at least two pairs of the clock signals, and a control circuit operable for adjusting delays caused by the programmable delay elements. The control circuit is operable for carrying out a de-skewing operation. The de-skewing operation comprises determining an order of occurrence of edges of the signals, selecting one of the programmable delay elements based on the determined order, and adjusting the delay caused by the selected programmable delay element.

The disclosure relates to a skew control circuit for controlling the skew between at least three clock signals, the clock signals being forwarded to different clock domains associated with the respective clock signals. The skew control circuit comprises multiple programmable delay elements arranged within a signal flow before the respective clock domain, a skew detector arrangement operable for detecting skews between at least two pairs of the clock signals, and a control circuit operable for adjusting delays caused by the programmable delay elements. The control circuit is operable for carrying out a de-skewing operation. The de-skewing operation comprises determining an order of occurrence of edges of the signals, selecting one of the programmable delay elements based on the determined order, and adjusting the delay caused by the selected programmable delay element.

The disclosure relates to a skew control circuit for controlling the skew between at least three clock signals, the clock signals being forwarded to different clock domains associated with the respective clock signals. The skew control circuit comprises multiple programmable delay elements arranged within a signal flow before the respective clock domain, a skew detector arrangement operable for detecting skews between at least two pairs of the clock signals, and a control circuit operable for adjusting delays caused by the programmable delay elements. The control circuit is operable for carrying out a de-skewing operation. The de-skewing operation comprises determining an order of occurrence of edges of the signals, selecting one of the programmable delay elements based on the determined order, and adjusting the delay caused by the selected programmable delay element.

A tri-stable storage loop useful in reciprocal quantum logic (RQL) gate circuits and systems has control and signal input lines. When alternating stable current storage states are induced in the storage loop by an alternating input provided to the control input line, provision of a positive SFQ pulse on the signal input line while the storage loop stores a positive current changes the storage loop from alternating between a positive-current state and a null-current state to alternating between a negative-current state and the null-current state, and provision of a negative SFQ pulse on the signal input line while the storage loop stores a negative current changes the storage loop from alternating between the negative-current state and the null-current state to alternating between the positive-current state and the null-current state.

A tri-stable storage loop useful in reciprocal quantum logic (RQL) gate circuits and systems has control and signal input lines. When alternating stable current storage states are induced in the storage loop by an alternating input provided to the control input line, provision of a positive SFQ pulse on the signal input line while the storage loop stores a positive current changes the storage loop from alternating between a positive-current state and a null-current state to alternating between a negative-current state and the null-current state, and provision of a negative SFQ pulse on the signal input line while the storage loop stores a negative current changes the storage loop from alternating between the negative-current state and the null-current state to alternating between the positive-current state and the null-current state.

Three state latch. In accordance with a first embodiment, an electronic circuit includes a single latch having three stable states. The electronic circuit may be configured so that all three outputs reflect a change at any one input in not more than three gate delays. The electronic circuit may further be configured so that when all inputs are set to one, a previous state of the latch is retained and output on the outputs.

Three state latch. In accordance with a first embodiment, an electronic circuit includes a single latch having three stable states. The electronic circuit may be configured so that all three outputs reflect a change at any one input in not more than three gate delays. The electronic circuit may further be configured so that when all inputs are set to one, a previous state of the latch is retained and output on the outputs.

Tri-state inverter includes a n-TFET and a p-TFET, the drain of the n-TFET being connected to the drain of the p-TFET and to an output of the tri-state inverter, the gates of the n-TFET and p-TFET being connected to an input of the tri-state inverter, and a control circuit able to apply a first control voltage on the source of the n-TFET and a second control voltage on the source of the p-TFET, the values of the first and second control voltages being positive or zero, wherein, when the tri-state inverter is intended to work as an inverter, the value of the first control voltage is lower than the value of the second control voltage, and when the tri-state inverter is intended to be tri-stated, the value of the first control voltage is higher than the value of the second control voltage.