A spike generation circuit includes a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input, a switch connected in series with the first CMOS inverter, between the first power supply and the second power supply, a first inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the switch, and a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated output spike signal to an output terminal.

Provided is a relaxation oscillating circuit, which comprises a charging circuit, a discharging circuit, a switch circuit, a charging-discharging capacitor and an output circuit. The charging circuit comprises a first current source and a first isolating transistor. The discharging circuit comprises a second current source and a second isolating transistor. The switch circuit comprises a main charging transistor and an auxiliary charging transistor arranged as mirror and a main discharging transistor and an auxiliary discharging transistor arranged as mirror. The main charging transistor and the main discharging transistor are alternately conducted. According to a voltage of the charging-discharging capacitor, the output circuit outputs a clock signal and a control signal. The clock signal is connected to control ends of the auxiliary charging transistor and the auxiliary discharging transistor, and the control signal is connected to control ends of the main charging transistor and the main discharging transistor.

An oscillator circuit includes a first comparator that outputs a first signal indicative of a comparison result between an input potential and a threshold, a second comparator that outputs a second signal indicative of a comparison result between an input potential and the threshold, a RS flip-flop circuit that receives the first signal and the second signal and outputs first and second oscillation signals, a first charge/discharge unit that charges and discharges a first capacitor based on the first oscillation signal, a second charge/discharge unit that charges and discharges a second capacitor based on the second oscillation signal, a first dummy switch controlled to be on and off according to the second oscillation signal and adding a predetermined capacity to a first node, and a second dummy switch controlled to be on and off according to the first oscillation signal and adding a predetermined capacity to a second node.

An oscillator circuit includes a first comparator that outputs a first signal indicative of a comparison result between an input potential and a threshold, a second comparator that outputs a second signal indicative of a comparison result between an input potential and the threshold, a RS flip-flop circuit that receives the first signal and the second signal and outputs first and second oscillation signals, a first charge/discharge unit that charges and discharges a first capacitor based on the first oscillation signal, a second charge/discharge unit that charges and discharges a second capacitor based on the second oscillation signal, a first dummy switch controlled to be on and off according to the second oscillation signal and adding a predetermined capacity to a first node, and a second dummy switch controlled to be on and off according to the first oscillation signal and adding a predetermined capacity to a second node.

[Object]

Adjusting oscillator characteristics.

[Solving Means]

An oscillation device includes multiple delay elements that each sequentially delay an input signal, and return at least some of the delayed signals to a preceding stage to generate an oscillation signal, and a first control terminal that inputs, to the multiple delay elements, a direct current control signal for collectively controlling direct current voltage levels of the input signal to be input in plural number to the multiple delay elements.

A signal correction circuit and a server are provided. The circuit comprises: a first signal processing component receiving an input signal and positive power supply voltages and negative power supply voltages, generating a first control voltage, and outputting a first voltage, the first voltage being zero within a first time period; a second signal processing component generating a second control voltage according to the first control voltage, performing energy storage charging according to the second control voltage, controlling an energy storage charging voltage according to the second control voltage, and outputting a second voltage, and the second voltage being zero in the second time period; and an output component performing superposition processing on the first voltage and the second voltage to obtain an output signal. In the disclosure, the ringback in an input signal can be eliminated, and in the circuit, a large amount of debugging and revision is not required.

A signal correction circuit and a server are provided. The circuit comprises: a first signal processing component receiving an input signal and positive power supply voltages and negative power supply voltages, generating a first control voltage, and outputting a first voltage, the first voltage being zero within a first time period; a second signal processing component generating a second control voltage according to the first control voltage, performing energy storage charging according to the second control voltage, controlling an energy storage charging voltage according to the second control voltage, and outputting a second voltage, and the second voltage being zero in the second time period; and an output component performing superposition processing on the first voltage and the second voltage to obtain an output signal. In the disclosure, the ringback in an input signal can be eliminated, and in the circuit, a large amount of debugging and revision is not required.

A spike generation circuit includes a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input, a switch connected in series with the first CMOS inverter, between the first power supply and the second power supply, a first inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the switch, and a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated output spike signal to an output terminal.

In described examples of an integrated circuit (IC), an oscillator includes Schmitt trigger delay cells connected in a ring topology. The Schmitt trigger delay cells have a high input threshold approximately equal to Vdd and a low input threshold approximately equal to Vss to increase delay through each cell. An output buffer receives a phase signal from an output terminal of one of the Schmitt trigger delay cells and converts a transition phase signal to a faster transition clock signal. The output buffer has control circuitry that generates non-overlapping control signals in response to the phase signal, to control an output stage to generate the fast transition clock signal while preventing short circuit current in the output stage.

In described examples of an integrated circuit (IC), an oscillator includes Schmitt trigger delay cells connected in a ring topology. The Schmitt trigger delay cells have a high input threshold approximately equal to Vdd and a low input threshold approximately equal to Vss to increase delay through each cell. An output buffer receives a phase signal from an output terminal of one of the Schmitt trigger delay cells and converts a transition phase signal to a faster transition clock signal. The output buffer has control circuitry that generates non-overlapping control signals in response to the phase signal, to control an output stage to generate the fast transition clock signal while preventing short circuit current in the output stage.