A level shifter includes a buffer circuit, a first shift circuit, and a second shift circuit. The buffer circuit provides a first signal and a first inverted signal to the first shift circuit, such that the first shift circuit provides a second signal and a second inverted signal to the second shift circuit. The second shift circuit generates a plurality of output signals according to the second signal and the second inverted signal. The first shift circuit includes a plurality of first stacking transistors and a first voltage divider circuit. The first voltage divider circuit is electrically coupled between a first system high voltage terminal and a system low voltage terminal. The first voltage divider circuit is configured to provide a first inner bias to gate terminals of the first stacking transistors.

A high-voltage tolerant circuit includes a first level shifter responsive to an input signal having a first logic high voltage and a first logic low voltage for providing a first intermediate signal having the first logic high voltage and a second logic low voltage referenced to a second reference voltage higher than the first logic low voltage, a second level shifter responsive to the input signal for providing a second intermediate signal having a second logic high voltage referenced to a first reference voltage lower than the first logic high voltage, and the first logic low voltage, an output stage responsive to the first and second intermediate signals for providing an output signal having the first logic high voltage and the first logic low voltage, and a reference voltage generation circuit providing the second logic high and second logic low voltages without drawing current from the reference voltage generation circuit.

A level shifter may include: a discharge circuit configured to receive an input signal on the basis of a first power supply voltage, and discharge an internal node on the basis of the input signal; a charge supply circuit configured to supply charge to an output node from which an output signal is outputted, on the basis of a second power supply voltage; and a voltage adjustment circuit including a first MOS transistor coupled between the internal node and the output node, and configured to adjust the voltage of the output node on the basis of a bias voltage applied to the first MOS transistor, and stop the operation of adjusting the voltage of the output node on the basis of the bias voltage, when the levels of the first and second power supply voltages are equal to each other.

Embodiments of the present disclosure provide a level shifter, including: first and second NMOS transistors, wherein the sources of the first and second NMOS transistors are coupled to a first voltage, the gate of the first NMOS transistor is connected to an inverse of an input signal that varies between a second voltage and a third voltage, and wherein the gate of the second NMOS transistor receives a buffer of the input signal. a breakdown protection circuit has third and fourth NMOS transistors, the gates of the third and fourth NMOS transistors being connected to the third voltage, the drain of the first NMOS transistor being connected to the source of the third NMOS transistor, and the drain of the second NMOS transistor being connected to the source of the fourth NMOS transistor. A pull-up circuit is connected to the drains of the third and fourth NMOS transistors.

A semiconductor device includes first, second, and third conductive regions and first and second active regions. The first conductive region has a first width and extends along a first direction. The second conductive region has a second width and extends along the first direction. The first width is greater than the second width. The first active region has a third width and extends along the first direction. The second active region has a fourth width and extends along the first direction. The third width is less than the fourth width. The third conductive region extends along a second direction and is electrically connected to the first conductive region. The second direction is different from the first direction. The first and second active regions are neighboring active regions.

A semiconductor device includes first, second, and third conductive regions and first and second active regions. The first conductive region has a first width and extends along a first direction. The second conductive region has a second width and extends along the first direction. The first width is greater than the second width. The first active region has a third width and extends along the first direction. The second active region has a fourth width and extends along the first direction. The third width is less than the fourth width. The third conductive region extends along a second direction and is electrically connected to the first conductive region. The second direction is different from the first direction. The first and second active regions are neighboring active regions.

The present disclosure relates to a dual-clock generation circuit and method and an electronic device, and relates to the technical field of integrated circuits. The dual-clock generation circuit includes: a first inverter module, configured to access a first signal and output a first clock output signal; a second inverter module, configured to access a second signal and output a second clock output signal, where the first signal and the second signal are opposite clock signals; a first feedforward buffer, disposed between an input terminal of the first inverter module and an output terminal of the second inverter module, and configured to transmit the first signal to compensate for the second clock output signal.

The present disclosure relates to a latch circuit and a latch method, and an electronic device, and relates to the technical field of integrated circuits. The latch circuit includes: a transmission module, a latch module, and a control module, wherein the transmission module is configured to transmit an input signal to the latch module; the latch module is configured to latch the input signal or output the input signal when a set signal or a reset signal is at a low level; and the control module is configured to perform control, such that a current leakage path cannot be formed between the transmission module and the latch module when the set signal or the reset signal is at a high level.

The present disclosure relates to a latch circuit and a latch method, and an electronic device, and relates to the technical field of integrated circuits. The latch circuit includes: a transmission module, a latch module, and a control module, wherein the transmission module is configured to transmit an input signal to the latch module; the latch module is configured to latch the input signal or output the input signal when a set signal or a reset signal is at a low level; and the control module is configured to perform control, such that a current leakage path cannot be formed between the transmission module and the latch module when the set signal or the reset signal is at a high level.

The present application provides a level shift circuit, an integrated circuit, and an electronic device. The level shift circuit comprises: an input module, configured to output a first control signal according to a first power supply voltage signal, first and second input voltages, inverted voltages of the first and second input voltages that received; a control voltage generation module, configured to receive the first control signal, and generate a plurality of node voltages according to the first control signal and a second power supply voltage signal; and output control modules, configured to generate first to fourth output signals according to the node voltages and the first power supply voltage signal, or generate fifth to eighth output signals according to the second power supply voltage signal and the node voltages.