A control method of an inverter for outputting polyphase alternate-current electrical power is provided. In the control method, modified PWM pulses of respective phases for controlling semiconductor switching elements of the inverter are generated, based on an output of a counter common to the respective phases. Each of the modified PWM pulses is configured such that a total pulse width, in a period corresponding to one or more cycles of a carrier, is substantially equal to a total pulse width of an assumed PWM pulse which is obtained by comparing, with the carrier, a time average value of an output voltage of the corresponding phase in the period. Further, at least one of a generation timing and a generation frequency of at least one of the modified PWM pulses is changed from the assumed PWM pulse.

A control method of an inverter for outputting polyphase alternate-current electrical power is provided. In the control method, modified PWM pulses of respective phases for controlling semiconductor switching elements of the inverter are generated, based on an output of a counter common to the respective phases. Each of the modified PWM pulses is configured such that a total pulse width, in a period corresponding to one or more cycles of a carrier, is substantially equal to a total pulse width of an assumed PWM pulse which is obtained by comparing, with the carrier, a time average value of an output voltage of the corresponding phase in the period. Further, at least one of a generation timing and a generation frequency of at least one of the modified PWM pulses is changed from the assumed PWM pulse.

An amplitude limiting oscillation circuit is disclosed. The amplitude limiting oscillation circuit includes: an oscillation circuit, configured to generate an oscillation signal; a pulse width modulation circuit, configured to generate a pulse width modulation signal according to an amplitude of the oscillation signal; a low pass filtering circuit, configured to convert the pulse width modulation signal into a direct current control voltage signal, where the direct current control voltage signal is configured to control a voltage controlled resistance circuit; and the voltage controlled resistance circuit, configured to change a resistance value of the voltage controlled resistance circuit according to under the direct current control voltage signal, to control the amplitude of the oscillation signal. The amplitude limiting oscillation circuit, may improve performance of the amplitude limiting oscillation circuit.

An amplitude limiting oscillation circuit is disclosed. The amplitude limiting oscillation circuit includes: an oscillation circuit, configured to generate an oscillation signal; a pulse width modulation circuit, configured to generate a pulse width modulation signal according to an amplitude of the oscillation signal; a low pass filtering circuit, configured to convert the pulse width modulation signal into a direct current control voltage signal, where the direct current control voltage signal is configured to control a voltage controlled resistance circuit; and the voltage controlled resistance circuit, configured to change a resistance value of the voltage controlled resistance circuit according to under the direct current control voltage signal, to control the amplitude of the oscillation signal. The amplitude limiting oscillation circuit, may improve performance of the amplitude limiting oscillation circuit.

In described examples, a sawtooth waveform generator generates a sawtooth waveform having a first rise time. A comb waveform circuit has a power terminal coupled to receive the sawtooth waveform from an output of the sawtooth waveform generator. The comb waveform circuit generates a comb waveform in response to the sawtooth waveform. The comb waveform has a second rise time that is faster than the first rise time.

In described examples, a sawtooth waveform generator generates a sawtooth waveform having a first rise time. A comb waveform circuit has a power terminal coupled to receive the sawtooth waveform from an output of the sawtooth waveform generator. The comb waveform circuit generates a comb waveform in response to the sawtooth waveform. The comb waveform has a second rise time that is faster than the first rise time.

Aspects provide for a circuit including a voltage supply, a driver, and a feedback bias circuit. The driver includes a first p-type field effect transistor (FET) and a first n-type FET. The voltage supply has an input and an output. The driver has a first input coupled to the voltage supply output, a second input coupled to a first node, and an output coupled to a second node. The first p-type FET has a gate coupled to the output of the driver, a source coupled to the voltage supply output, and a drain coupled to the second node. The first n-type FET has a gate coupled to the output of the second driver, a drain coupled to the second node, and a source coupled to a ground node. The feedback bias circuit has an input coupled to the second node and an output coupled to the voltage supply input.

Aspects provide for a circuit including a voltage supply, a driver, and a feedback bias circuit. The driver includes a first p-type field effect transistor (FET) and a first n-type FET. The voltage supply has an input and an output. The driver has a first input coupled to the voltage supply output, a second input coupled to a first node, and an output coupled to a second node. The first p-type FET has a gate coupled to the output of the driver, a source coupled to the voltage supply output, and a drain coupled to the second node. The first n-type FET has a gate coupled to the output of the second driver, a drain coupled to the second node, and a source coupled to a ground node. The feedback bias circuit has an input coupled to the second node and an output coupled to the voltage supply input.

A system is provided for generating a ramping signal. The system includes a plurality of storage circuits each including an input and an output. The output of a previous storage circuit is connected to the input of a next storage circuit. The storage circuits are configured to propagate a first enable signal based on a first control signal. The system also includes a plurality of first current generating circuits. Each first current generating circuit is coupled to the output of a corresponding storage circuit to receive the propagated first enable signal. The first current generating circuits are configured to generate a first current signal based on the propagated first enable signal.

A system is provided for generating a ramping signal. The system includes a plurality of storage circuits each including an input and an output. The output of a previous storage circuit is connected to the input of a next storage circuit. The storage circuits are configured to propagate a first enable signal based on a first control signal. The system also includes a plurality of first current generating circuits. Each first current generating circuit is coupled to the output of a corresponding storage circuit to receive the propagated first enable signal. The first current generating circuits are configured to generate a first current signal based on the propagated first enable signal.